Machine Learning Drives High-Level Synthesis Boom


High-level synthesis (HLS) is experiencing a new wave of popularity, driven by its ability to handle machine-learning matrices and iterative design efforts. The obvious advantage of HLS is the boost in productivity designers get from working in C, C++ and other high-level languages rather than RTL. The ability to design a layout that should work, and then easily modify it to test other confi... » read more

Challenges In Using HLS For FPGA Design


High-level synthesis (HLS) tools, which transform C/C++ source code to Verilog/VHDL, have been commercially available for over 15 years. HLS tools from FPGA vendors and EDA companies promise improved productivity through a higher-level of abstraction, faster verification and quicker design iterations. For example, simulating your design in C/C++ can be 10 to 100x faster than simulating in RTL (... » read more

Smoke Testing A High-Level Synthesis Design


Designing hardware using C++ and C++ testbenches brings orders of magnitude speed-up to simulation. But after High-Level Synthesis (HLS), teams need a way to quickly ensure that the newly-generated RTL is functionally the same as the original untimed C++. They don’t want to create an RTL testbench in order to make this comparison. What teams need is an automated smoke test to quickly make the... » read more

Chip Industry In Rapid Transition


Wally Rhines, CEO Emeritus at Mentor, a Siemens Business, sat down with Semiconductor Engineering to talk about global economics, AI, the growing emphasis on customization, and the impact of security and higher abstraction levels. What follows are excerpts of that conversation. SE: Where do you see the biggest changes happening across the chip industry? Rhines: 2018 was a hot year for fab... » read more

Formal Datapath Verification


J.T. Longino, formal verification application engineer at Synopsys, drills down into how to achieve confidence in datapath designs by applying formal solvers and methods to data transformation areas of a design rather than the control path areas. https://youtu.be/n1zO3GxEZVI     See other tech talk videos here. » read more

Verification As A Flow (Part 2)


Semiconductor Engineering sat down to discuss the transformation of verification from a tool to a flow with Vladislav Palfy, global manager application engineering for OneSpin Solutions; Dave Kelf, chief marketing officer for Breker Verification Systems; Mark Olen, product marketing group manager for Mentor, A Siemens Business; Larry Melling, product management director, System & Verificati... » read more

An Easier Path To Faster C With FPGAs


For most scientists, what is inside a high-performance computing platform is a mystery. All they usually want to know is that a platform will run an advanced algorithm thrown at it. What happens when a subject matter expert creates a powerful model for an algorithm that in turn automatically generates C code that runs too slowly? FPGA experts have created an answer. More and more, the genera... » read more

How High-Level Synthesis Was Used To Develop An Image-Processing IP Design From C++ Source Code


Imagine working long and hard on a design, only to learn that you need to add new (and more complex) functionality a few months before your targeted tapeout. How can you deliver the performance and capabilities expected in the same timeframe? For Bosch, high-level synthesis (HLS) provided the solution. In this paper, we will discuss how HLS technology enabled the team to meet an aggressive sche... » read more

Development Testing For C# Applications


Static analysis shouldn’t be about finding loads of coding style or standard issues. It should be focused on finding the most critical defects. Although traditional byte code analysis solutions such as FxCop are useful, they can miss critical, crash causing defects - plus produce a large set of coding style issues, which can slow down the development team. Learn how the Coverity Development T... » read more

Can Verification Meet In The Middle?


Since the dawn of time for the EDA industry, the classic V diagram has defined the primary design flow. On the left hand side of the V, the design is progressively refined and partitioned into smaller pieces. At the bottom of the V, verification takes over and as you travel up the right-hand side of the V, verification and integration happens until the entire design has been assembled and valid... » read more

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