tag: C++

The Evolution Of High-Level Synthesis
By Brian Bailey - 27 Aug, 2020 - Comments: 3

High-level synthesis is getting yet another chance to shine, this time from new markets and new technology nodes. But it's still unclear how fully this technology will be used. Despite gains, it remains unlikely to replace the incumbent RTL design methodology for most of the chip, as originally expected. Seen as the foundational technology for the next generation of EDA companies around the ... » read more

Universal Verification Methodology Running Out Of Steam
By Ann Mutschler - 30 Jul, 2020 - Comments: 2

For the past decade or so, the Universal Verification Methodology (UVM) has been the de facto verification methodology supported by the entire EDA industry. But as chips become more heterogeneous, more complex, and significantly larger, UVM is running out of steam. Consensus is building that some fundamental changes are required, moving tools up a level of abstraction and making them more ag... » read more

The Trouble With Semantics
By Brian Bailey - 30 Jan, 2020 - Comments: 2

Semantics are important. They tell us what something means. Without semantics you just have a jumble of syntax. The better defined the semantics are, the less likely something is to be mis-interpreted because they can be more rigidly analyzed. The semantics of the English language are not very well defined, which is why it is impossible to write a specification where everyone agrees upon wha... » read more

Divided On System Partitioning
By Brian Bailey - 30 Jan, 2020 - Comments: 0

Building an optimal implementation of a system using a functional description has been an industry goal for a long time, but it has proven to be much more difficult than it sounds. The general idea is to take software designed to run on a processor and to improve performance using various types of alternative hardware. That performance can be specified in various ways and for specific applic... » read more

Optimizing Hardware Faster
By Ed Sperling - 26 Nov, 2019 - Comments: 0

Maximillian Odendahl, CEO of Silexica, sat down with Semiconductor Engineering to talk about high-level synthesis and the changing role of this technology. What follows are excerpts of that conversation. SE: What is the direction that high-level synthesis is heading in? Odendahl: The direction hasn’t changed, but in the past HLS was not usable by the software guys. The main push right n... » read more

Power/Performance Bits: Oct. 15
By Jesse Allen - 15 Oct, 2019 - Comments: 0

Probabilistic computing Researchers at Purdue University and Tohoku University built a hardware demonstration of a probabilistic computer utilizing p-bits to perform quantum computer-like calculations. The team says probabilistic computing could bridge the gap between classical and quantum computing and more efficiently solve problems in areas such as drug research, encryption and cybersecurit... » read more

High-Level Design And High-Level Verification
By Dominik Strasser - 26 Sep, 2019 - Comments: 0

Not so long ago, some EDA vendors were painting a very attractive picture of chip design in the then-near future. The idea was that an architectural team would write a single description of the complete system in some high-level language, usually C/C++/SystemC, and that a new class of EDA tool would automatically partition the design into hardware and software, choosing the functionality of eac... » read more

Synthesizing Hardware From Software
By Brian Bailey - 22 Aug, 2019 - Comments: 1

The ability to automatically generate optimized hardware from software was one of the primary tenets of system-level design automation that was never fully achieved. The question now is whether that will ever happen, and whether it is just a matter of having the right technology or motivation to make it possible. While high-level synthesis (HLS) did come out of this work and has proven to be... » read more

High-Level Synthesis For Autonomous Drive
By Mentor, a Siemens Business - 31 Jul, 2019 - Comments: 0

The sensors in autonomous vehicles continuously generate a high volume of data in real time about the environment surrounding the car. The vehicles need new hardware architectures to be able to process this data quickly and make decisions that enable self driving. Catapult, the industry’s leading High-Level Synthesis (HLS) platform, provides a new paradigm of designing silicon at a higher lev... » read more

Konica Minolta Proves C++ Level Signoff Possibilities Using Catapult HLS Platform
By Mentor, a Siemens Business - 24 Jul, 2019 - Comments: 0

A team’s ultimate goal is to move verification up to the C++ level in order to minimize the time spent in RTL verification and to achieve C++ signoff. A team at Konica Minolta® has been using the Catapult HLS Platform for many years to dramatically improve their productivity by coding at the C++ level and using the platform to generate RTL. They recently evaluated the high-level verification... » read more

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