Automotive OEMs Focus On SDVs, Zonal Architectures


Giant automotive OEMs are re-evaluating how quickly to move to advanced technologies and software-driven designs amid crushing financial pressure from low-cost EVs developed in other markets such as China. U.S., European, and Japanese OEMs have been struggling for the past half-decade or so to figure out which is the best approach to developing EVs, undergoing multiple shifts in both hardwar... » read more

Data Routing In Heterogeneous Chip Designs


Ensuring data gets to where it's supposed to go at exactly the right time is a growing challenge for design engineers and architects developing heterogeneous systems. There is more data moving around these chips with dozens of targets, which makes routing signals much more complicated. Ronen Perets, senior product marketing manager at Cadence Design Systems, talks about some of the new problems... » read more

Intel and Cadence Collaboration on UCIe: Demonstration of Simulation Interoperability


The Universal Chiplet Interconnect Express (UCIe) 1.0 specification was announced in early 2022. A new updated UCIe 1.1 specification was released on August 8, 2023. The standardized open chiplet standard allows for heterogeneous integration of die-to-die link interconnects within the same package. The UCIe standard allows for advanced package and standard package options to tradeoff cost, band... » read more

Chip Industry Week In Review


Chinese firms imported almost $26 billion worth of chipmaking machinery, according to fresh trade data released by China’s General Administration of Customs this week, Bloomberg reports. Meanwhile, the global semiconductor manufacturing industry continued to show signs of improvement in Q2 2024 with significant growth of IC sales, stabilizing capital expenditure, and an increase in install... » read more

Sensor Fusion Challenges In Automotive


The number of sensors in automobiles is growing rapidly alongside new safety features and increasing levels of autonomy. The challenge is integrating them in a way that makes sense, because these sensors are optimized for different types of data, sometimes with different resolution requirements even for the same type of data, and frequently with very different latency, power consumption, and re... » read more

Quantum Well Design Basics


Key Takeaways The choice of materials for the quantum well and barrier layers is paramount. Materials must have compatible lattice structures to minimize defects, with common combinations including GaAs/AlGaAs, InGaAs/InP, and GaN/AlGaN. The width of the quantum well significantly influences the energy levels and density of states, where narrower wells result in greater separation betwe... » read more

Cadence Cerebrus In SaaS And Imagination Technologies Case Study


Artificial Intelligence (AI) has made noteworthy progress and is now ready and available for electronic design automation. The Cadence Cerebrus Intelligent Chip Explorer utilizes AI—specifically, reinforcement machine learning (ML) technology—combined with the industry-leading Cadence digital full flow to deliver better power, performance, and area (PPA) more quickly. However, this highl... » read more

3D Connection Artifacts In PDN Measurements


Authors: Ethan Koether, Amazon; Kristoffer Skytte, John Phillips, Shirin Farrahi, Cadence; Joseph Hartman, Oracle; Sammy Hindi, Ampere Computing Inc.; Mario Rotigni, STMicroelectronics; Gustavo Blando, Istvan Novak, Samtec From a simulation stand-point, we have covered several important topics that users must consider in detail to get accurate low frequency simulation results. We investigate... » read more

Expecting The Unexpected: Analyzing A Data Center Cooling Failure


Data center thermal management is often a reactive process. Servers issue warning messages, monitoring alarms activate, or employees express concern about general temperature levels/hotspots and then management decides what to do next. For incremental issues, once known, the necessary steps can be taken to resolve or improve these issues; however, what happens when a potential thermal issue onl... » read more

Machine Learning Based MBIST Area Estimation


Majority of the silicon with-in a design is occupied by memories. Memories are more prone to failures than logic due to their density. Several techniques have been established to target and detect defects within these memory instances and their interfacing logic. The most widely used approach is memory built-in self-test (MBIST) that inserts on-chip hardware unit(s) which provides systematic me... » read more

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