tag: Cadence Design Systems

The Physics Of Ports And Associated Ground For EM Simulators Serving RF Designs
By Cadence - 09 Dec, 2021 - Comments: 0

The use of ports in electromagnetic (EM) simulators has evolved and matured over the years to make real-world design simulations practical. Having a foundational understanding of ports provides an intuitive skill in their proper selection and use in conjunction with circuit simulation. In this white paper, we examine ports common to EM simulators, which are the most common simulators for microw... » read more

Improving Energy And Power Efficiency In The Data Center
By Ann Mutschler - 06 Dec, 2021 - Comments: 0

Energy costs in data centers are soaring as the amount of data being generated explodes, and it's being made worse by an imbalance between increasingly dense processing elements that are producing more heat and uneven server utilization, which requires more machines to be powered up and cooled. The challenge is to maximize utilization without sacrificing performance, and in the past that has... » read more

Why It’s So Difficult — And Costly — To Secure Chips
By Ed Sperling - 02 Dec, 2021 - Comments: 0

Rising concerns about the security of chips used in everything from cars to data centers are driving up the cost and complexity of electronic systems in a variety of ways, some obvious and others less so. Until very recently, semiconductor security was viewed more as a theoretical threat than a real one. Governments certainly worried about adversaries taking control of secure systems through... » read more

Advanced Packaging For Automotive Chips
By Ann Mutschler - 02 Dec, 2021 - Comments: 0

Multiple types of chips may be better than one for dealing with large amounts and different types of data, but in automotive applications it's not entirely clear how or even whether they should be packaged together. The biggest problem with electronics in vehicles is the extreme range of temperatures, both within and outside of vehicles. Without adequate cooling, chips can age prematurely, s... » read more

Will Markets For ML Models Materialize?
By Bryon Moyer - 02 Dec, 2021 - Comments: 0

Developers are spending increasing amounts of time and effort in creating machine-learning (ML) models for use in a wide variety of applications. While this will continue as the market matures, at some point some of these efforts might be seen as reinventing models over and over. Will developers of successful models ever have a marketplace in which they can sell those models as IP to other d... » read more

Missing Interposer Abstractions And Standards
By Brian Bailey - 29 Nov, 2021 - Comments: 0

The design and analysis of an SoC based on an interposer is not for the faint of heart today, but the industry is aware of the challenges and is attempting to solve them. Until that happens, however, it will be a technique that only large companies can deploy because they need to treat everything almost as if it were a single die. The construction of large systems uses techniques, such as ab... » read more

Product Lifecycle Management For Semiconductors
By Brian Bailey - 23 Nov, 2021 - Comments: 1

Product lifecycle management (PLM) and the semiconductor industry have always been separate, but pressure is growing to integrate them. Automotive, IIoT, medical, and other industries see that as the only way to manage many aspects of their business, and as it stands, semiconductors are a large black box in that methodology. The technology space is driven by a mix of top down and bottom-up p... » read more

Advanced Packaging Shifts Design Focus To System Level
By Ann Mutschler - 23 Nov, 2021 - Comments: 0

Growing momentum for advanced packaging is shifting design from a die-centric focus toward integrated systems with multiple die, but it's also straining some EDA tools and methodologies and creating gaps in areas where none existed. These changes are causing churn in unexpected areas. For some chip companies, this has resulted in a slowdown in hiring of ASIC designers and an uptick in new jo... » read more

Interop Shift Left: Using Pre-Silicon Simulation for Emerging Standards
By Cadence - 22 Nov, 2021 - Comments: 0

The Compute Express Link (CXL) 2.0 specification, released in 2020, accompanies the latest PCI Express (PCIe) 5.0 specification to provide a path to high-bandwidth, cache-coherent, low-latency transport for many high-bandwidth applications such as artificial intelligence, machine learning, and hyperscale applications, with specific use cases in newer memory architectures such as disaggregated a... » read more

Week In Review: Auto, Security, Pervasive Computing
By Susan Rambo - 19 Nov, 2021 - Comments: 0

3D-ICs Samsung Foundry released 3D-IC EDA flows approvals. 3D-ICs, which are the multi-dies stacked together and integrated into a package, are finding use in automotive, high-performance computing, and artificial intelligence systems. Samsung Foundry qualified Cadence’s 2D-to-3D native 3D partitioning flow for 3D-IC design that automates creating a memory-on-logic 3D stacking configuration,... » read more

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