tag: Cadence Design Systems

Week In Review: Auto, Security, Pervasive Computing
By Susan Rambo - 12 Jun, 2020 - Comments: 0

Edge, cloud, data center Programmable logic company Efinix used Cadence’s Digital Full Flow to finish Efinix’s Trion FPGA family for edge computing, AI/ML and vision processing applications, according to a press release. Last week Efinix also announced three software defined SoCs based on the RISC-V core. The SoCs are optimized to the Trion FPGAs. AI, machine learning Amazon will tempo... » read more

Best Full-Flow PPA
By Cadence - 10 Jun, 2020 - Comments: 0

In the past few years, Cadence revolutionized the way digital designers could solve their design challenges by revamping the entire digital tool suite with key enhancements such as integrated engines, massively parallel processing, and early signoff optimization, all delivering faster turnaround time and best-in-class power, performance, and area (PPA) optimization. In the era of FinFETs and ad... » read more

Week In Review: Auto, Security, Pervasive Computing
By Susan Rambo - 05 Jun, 2020 - Comments: 0

Edge, cloud, data center Synopsys launched its USB4 IP and tools, already with a successful tapeout of a USB4 PHY test chip on 5nm advanced FinFET process. The Designware USB4 IP’s throughput is up to 20 or 40 Gbps, which Synopsys says is the bandwidth needed for high-performance edge AI, storage, PC, and tablet SoC designs. Also, Samsung Foundry certified Synopsys’ Design Compiler NXT for ... » read more

Computational Software
By Cadence - 03 Jun, 2020 - Comments: 0

To power the technologies and products of the future, end-application system companies are increasingly designing the full stack of their solution. Some are even designing their own semiconductors, and optimizing the end-to-end solution across chips, packages, printed circuit boards (PCBs), software, and the entire system to meet demanding market requirements. This movement is driving a converg... » read more

Week In Review: Auto, Security, Pervasive Computing
By Susan Rambo - 29 May, 2020 - Comments: 0

An effort to fund U.S. science and technology initiatives with at least $100 billion is getting a thumbs up from the SIA (Semiconductor Industry Association). The Endless Frontier Act —  a bipartisan, bicameral bill introduced on Thursday in the U.S. House of Representatives — will invest money into semiconductor research and development and other related fields such as material science, q... » read more

Plan-Based Analog Verification Methodology
By Cadence - 27 May, 2020 - Comments: 0

The ability to verify all the aspects of an analog design and to keep track of all the different verification tasks is a growing challenge. Manual attempts to do so often lead to mistakes since they rely on constantly updated documents. The Cadence Virtuoso ADE Verifier provides an overarching verification plan that links to all analog tests across multiple designers. The Virtuoso ADE Verifier ... » read more

Week In Review: Auto, Security, Pervasive Computing
By Susan Rambo - 22 May, 2020 - Comments: 0

Edge, cloud, data center Cadence added new verification IP (VIP) for hyperscalar data centers that supports CXL – Compute Express Link, HBM3, and Ethernet 802.3ck. The VIP are part of Cadence’s Verification Suite. Cadence also released IP for 56G long-reach SerDes on TSMC’s N7 and N6 process technologies. Many Mentor, a Siemens Business, IC design tools are now certified TSMC’s N5 a... » read more

Sensing Automotive IC Failures
By Anne Meixner - 12 May, 2020 - Comments: 1

The sooner you detect a failure in any electronic system, the sooner you can act. Together, data analytics and on-chip sensors are poised to boost quality in auto chips and add a growing level of predictive maintenance for vehicles. The ballooning number of chips cars makes it difficult to reach 10 defective parts per billion for every IC that goes into a car.  And requiring that for a 15-y... » read more

Inference Moves To The Network
By Bryon Moyer - 07 May, 2020 - Comments: 0

Machine-learning inference started out as a data-center activity, but tremendous effort is being put into inference at the edge. At this point, the “edge” is not a well-defined concept, and future inference capabilities will reside not only at the extremes of the data center and a data-gathering device, but at multiple points in between. “Inference isn't a function that has to resid... » read more

Improving Test Coverage And Eliminating Test Ecapes Using Analog Defect Analysis
By Cadence - 06 May, 2020 - Comments: 0

While the analog and mixed-signal components are the leading source of test escapes that result in field failures, the lack of tools to analyze the test coverage during design has made it difficult for designers to address the issue. In this white paper, we explore the methodology for performing analog fault simulation of test coverage based on defect-oriented testing. In addition, we look at h... » read more

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