tag: Cadence Design Systems

Week In Review: Auto, Security, Pervasive Computing
By SE Staff - 22 May, 2020 - Comments: 0

Edge, cloud, data center Cadence added new verification IP (VIP) for hyperscalar data centers that supports CXL – Compute Express Link, HBM3, and Ethernet 802.3ck. The VIP are part of Cadence’s Verification Suite. Cadence also released IP for 56G long-reach SerDes on TSMC’s N7 and N6 process technologies. Many Mentor, a Siemens Business, IC design tools are now certified TSMC’s N5 a... » read more

Sensing Automotive IC Failures
By Anne Meixner - 12 May, 2020 - Comments: 1

The sooner you detect a failure in any electronic system, the sooner you can act. Together, data analytics and on-chip sensors are poised to boost quality in auto chips and add a growing level of predictive maintenance for vehicles. The ballooning number of chips cars makes it difficult to reach 10 defective parts per billion for every IC that goes into a car.  And requiring that for a 15-y... » read more

Inference Moves To The Network
By Bryon Moyer - 07 May, 2020 - Comments: 0

Machine-learning inference started out as a data-center activity, but tremendous effort is being put into inference at the edge. At this point, the “edge” is not a well-defined concept, and future inference capabilities will reside not only at the extremes of the data center and a data-gathering device, but at multiple points in between. “Inference isn't a function that has to resid... » read more

Improving Test Coverage And Eliminating Test Ecapes Using Analog Defect Analysis
By Cadence - 06 May, 2020 - Comments: 0

While the analog and mixed-signal components are the leading source of test escapes that result in field failures, the lack of tools to analyze the test coverage during design has made it difficult for designers to address the issue. In this white paper, we explore the methodology for performing analog fault simulation of test coverage based on defect-oriented testing. In addition, we look at h... » read more

Power-Hungry Safety And Security
By Brian Bailey - 09 Apr, 2020 - Comments: 0

There is a price to pay for everything. When it comes to adding safety and security into a device, the costs in terms of power and area can be significant, but if the task is taken seriously, those costs can be managed and minimized. New analysis and implementation tools are coming to market that can also help to keep the costs contained. But it also requires the right mindset. As more indus... » read more

Intelligent System Design
By Cadence - 25 Mar, 2020 - Comments: 0

Electronics technology is proliferating to new, creative applications and appearing in our everyday lives. To compete, system companies are increasingly designing their own semiconductor chips, and semiconductor companies are delivering software stacks, to enable substantial differentiation of their products. This trend started in mobile devices and is now moving into cloud computing, automotiv... » read more

Week In Review: Auto, Security, Pervasive Computing
By SE Staff - 20 Mar, 2020 - Comments: 0

National Instruments is offering free online training courses to anyone anywhere, until the end of April to help support the engineering community during COVID-19 crisis. Some instructor-led virtual training is available at reduced cost. NIWeek has been postponed this year until August 3-5, 2020. Click here for more news about how the semiconductor industry is handling COVID-19. AI, machi... » read more

Week In Review: Auto, Security, Pervasive Computing
By SE Staff - 13 Mar, 2020 - Comments: 0

AI, machine learning Cadence says it has optimized its Tensilica HiFi digital signal processor IP to efficiently execute TensorFlow Lite for Microcontrollers, which are used in Google’s machine learning platform for edge. This means developers of AI/ML on the edge systems can now put better audio processing on edge devices with ML applications like keyword detection, audio scene detection, n... » read more

System-Level Electro-Thermal Analysis of RDS(ON) for Power MOSFET
By Cadence - 11 Mar, 2020 - Comments: 0

Authors: Rajen Murugan1, Nathan Ai2, and C.T. Kao2 1 Texas Instruments, Inc., Dallas, Texas, 75044, USA 2 Cadence Design Systems, Santa Clara, California, USA A coupled-electro-thermal RDS(ON) (drain to source ON resistance) co-analysis methodology for Power MOSFET is proposed. The methodology contains two functional modules: 1) physical field solvers and 2) equivalent circuit/network so... » read more

A Tipping Point For Women In Semiconductors
By SE Staff - 09 Mar, 2020 - Comments: 0

Yesterday was International Women’s Day, which for some people was a day of protest and action to raise awareness of issues that women face around the world. The day was more than just a feel-good Google doodle that blipped across our screens on Sunday: women were out in the streets getting arrested, tear gassed, and sprayed with water hoses. In some countries, the risk of openly walking with... » read more

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