tag: Cadence

The Problem With Post-Silicon Debug
By Ann Mutschler - 28 Feb, 2019 - Comments: 0

Semiconductor engineers traditionally have focused on trying to create 'perfect' GDSII at tape-out, but factors such as hardware-software interactions, increasingly heterogeneous designs, and the introduction of AI are forcing companies to rethink that approach. In the past, chipmakers typically banked on longer product cycles and multiple iterations of silicon to identify problems. This no ... » read more

Can Debug Be Tamed?
By Brian Bailey - 28 Feb, 2019 - Comments: 0

Debug consumes more time than any other aspect of the chip design and verification process, and it adds uncertainty and risk to semiconductor development because there are always lingering questions about whether enough bugs were caught in the allotted amount of time. Recent figures suggest that the problem is getting worse, too, as complexity and demand for reliability continue to rise. The... » read more

Unified Compression and LBIST in a Physically Aware Environment
By Cadence - 27 Feb, 2019 - Comments: 0

Unified compression is a new approach that unifies scan compression and logic built-in self-test (LBIST). It leverages recent innovations from Cadence in physically-aware design for test (DFT) to solve routing congestion and area issues from traditional discrete approaches and delivers a confident path to high-quality test. On a sample design, area savings of 35–47%, and scan wirelength savin... » read more

Blog Review: Feb. 27
By Jesse Allen - 27 Feb, 2019 - Comments: 0

Mentor's Harry Foster checks out the trends in language and library adoption for IC/ASIC designs and finds increased adoption of SystemVerilog for both design and verification while UVM remains the dominant verification methodology. Synopsys' Taylor Armerding chats with Chris Clark of Synopsys and Tim Weisenberger of SAE about the weakest points in automotive security and why it's time to mo... » read more

Partitioning Drives Architectural Considerations
By Ann Mutschler - 25 Feb, 2019 - Comments: 0

Semiconductor Engineering sat down to explore partitioning with Raymond Nijssen, vice president of system engineering at Achronix; Andy Ladd, CEO at Baum; Dave Kelf, chief marketing officer at Breker; Rod Metcalfe, product management group director in the Digital & Signoff Group at Cadence; Mark Olen, product marketing group manager at Mentor, a Siemens Business; Tom Anderson, technical mar... » read more

Week In Review: Design, Low Power
By Jesse Allen - 22 Feb, 2019 - Comments: 0

Tools OneSpin unveiled a set of formal apps for development and assessment of RISC-V cores. The RISC-V Integrity Verification Solution formalizes the RISC-V ISA in a set of SystemVerilog Assertions to verify compliance for the ISA is met. It provides a formal bug absence core assessment environment for unbounded proofs and systematic discovery of all hidden instructions or unintended side effe... » read more

Blog Review: Feb. 20
By Jesse Allen - 20 Feb, 2019 - Comments: 0

Synopsys' Chirag Tyagi examines how Display Stream Compression 1.2 allows the commonly used MIPI DSI display interface to support 8k UHD displays in applications like infotainment and AR/VR even with the limited bandwidth of PHY layers. Cadence's Paul McLellan listens in on a panel discussion at DesignCon on how to create PDKs for silicon photonics so non-photonics experts can complete at le... » read more

Week In Review: Design, Low Power
By SE Staff - 15 Feb, 2019 - Comments: 0

Tools & IP Engineering simulation company ANSYS says thanks to new features in its ANSYS Twin Builder, product developers may be able save money in warranty and operational costs. The Twin Builder creates a digital twin of a systems in the field, enabling a convenient way to monitor and maintain systems remotely. The latest release adds predictive maintenance features for digital-twin runt... » read more

Gearing Up For 5G
By Brian Bailey - 14 Feb, 2019 - Comments: 0

5G has been touted as the new enabler for many market segments, including mobile phones, automotive, virtual reality, and IoT. But there are many questions and much speculation about when and how this new wireless standard will impact different market segments and what effect it will have on semiconductor design. With a promise of orders of magnitude improvement in communication speed an... » read more

Why Analog Designs Fail
By Brian Bailey - 14 Feb, 2019 - Comments: 2

The gap between analog and digital reliability is growing, and digital designs appear to be winning. Reports show that analog content causes the most test failures and contributes significantly more than digital to field returns. The causes aren't always obvious, though. Some of it is due to the maturity of analog design and verification. While great strides have been made in digital circuit... » read more

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