Week In Review: Design, Low Power

Digital twins for systems maintenance; Arm’s Helium for v8.1-M; multicore SoC analytics; regression run dashboards in the cloud


Tools & IP
Engineering simulation company ANSYS says thanks to new features in its ANSYS Twin Builder, product developers may be able save money in warranty and operational costs. The Twin Builder creates a digital twin of a systems in the field, enabling a convenient way to monitor and maintain systems remotely. The latest release adds predictive maintenance features for digital-twin runtime generation and model export for IIoT (Industrial Internet of Things) platforms. The software reuses existing 3D simulation models to reduce storage needs and speed up simulations. ANSYS says users can quickly modify digital twins of deployed assets and “mirror altered or upgraded field equipment, such as pumps, motors and turbines, to better perform predictive maintenance.”

Arm has announced it will add Helium, an M-Profile Vector Extension (MVE) to its v8.1-M architecture to make machine learning and signal processing less complicated for small, power constrained embedded systems that need to process data locally. Armv8.1-M with Helium will provide real-time control code, ML and DSP execution without compromising efficiency, says the company. The configuration removes the need for a separate digital signal processor. The Helium toolchain includes Arm Development Studio, Arm Models and software libraries such as CMSIS-DSP and CMSIS-NN.

UltraSoc is adding more data analytics capabilities to its new SoC IDE (integrated development Environment) UltraDevelop 2 for monitoring unlimited internal building blocks and analyzing their impact on system-level behavior. Because of the complexity of artificial intelligence systems and heterogenous multicore SoCs, SoC designers frequently don’t have visibility into the interactions among the blocks, making debugging difficult. SoC designers will be able to build analytics monitoring systems up to 65,000 elements for thousands of processors, but eventually UltraSoc plans extend the number of processors for Exascale systems. UltraSoc says its system memory buffer IP will enable its analytics infrastructure to process the high volumes of data generated by multicore systems. The new analytics capabilities will be rolled out to customers in Q1 2019.

Metrics Technologies has added new capabilities to its cloud-based Metrics Platform for ASIC and complex FPGA design verification. The platform uses Google Cloud and a SaaS (software as a service) model for simulating SystemVerilog-based designs, managing the data and team workflows via a Git Workflow. The company has added a dashboard to collect a project’s vital statistics from all the regression runs, along with access to an online verification tool that helps users analyze simulation data with coverage reporting and regression debug tools. Users can eliminate redundant regression simulations through a ranking that an expanded version of the built-in regression analysis will do automatically. Metrics Technologies will demo new features at DVCon 2019.

SmartDV Technologies has unveiled its SimXL, a portfolio of synthesizable transactors for system-level, SoC testing on hardware emulators or FPGA prototyping platforms. SmartDV says in an emailed press release that SimXL is a configurable, reusable plug-and-play verification tool for interfaces based on industry-standard hardware verification languages. It runs on many of the standard systems, from Cadence, Synopsys and Mentor, a Siemens Business. SmartDV will demo SimXL at DVCon 2019.

National Instruments has appointed its first chief marketing officer (CMO). Marketing veteran Carla Piñeyro Sublett has been named as CMO, where she will lead efforts to elevate the company’s global brand, customer engagement and lead generation. She is the former CMO at Rackspace and at Dell held executive roles in sales and marketing.

Deals & partnerships
Avera Semi, a subsidiary of Globalfoundries, has selected Cadence as its primary EDA tool vendor, according to a press release. Avera Semi tapes out advanced node chip design projects, including in several large, complex 12nm and 14nm tapeouts.

eFPGA vendor Achronix Semiconductor Corporation has created a partner program for its Speedster, Speedchip, and Speedcore Ecosystems. The program is intended to help participating partners connect with each other. “Through the Achronix Partner Program, we have committed to giving customers easy access to a broad, growing, and robust ecosystem of EDA and IP partners, who can provide products and services that will speed the design of systems based on Achronix’s programmable logic devices and IP,” said Steve Mensor, vice president of marketing at Achronix.

As a member of the O-RAN Alliance, Keysight is collaborating with other O-RAN members AT&T, Anokiwave, Ball Corporation and Xilinx to develop 5G networks that use an open radio access network (O-RAN) architecture. The fruit of the collaboration so far is a demo of an O-RAN 5G mmWave radio unit white box using the open, interoperable interfaces. The open radio access network is an open-source standards effort to get consensus and that clarity around what off-the-shelf parts are ready or need to be designed for 5G networks.

Synopsys has announced that its Simpleware ScanIP Medical has a CE marking for the EEA (European Economic Area) and FDA 510(k) clearance, two regulatory certifications. Simpleware takes 3D scan data and converts it into computer models for design and simulation.

DVCon 2019: Feb. 25-28 in San Jose, CA. This year’s keynote will argue why it’s important to have an integrated digitalization strategy. Other highlights include a tutorial covering new features in IEEE 1800.2-UVM, a workshop on functional coverage in SystemC, and panels on deep learning and the verification of open ISAs.

DATE 2019: Mar. 25-29 in Florence, Italy. The conference and exhibition will feature keynotes on heterogeneous computing in cloud and HPC as well as the limitations of modeling frameworks for intelligent systems. Sessions will highlight emerging design technologies, design and test of secure systems, embedded systems for deep learning, and more. Advanced registration closes Mar. 13

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