tag: Cadence

Week In Review: Design, Low Power
By Jesse Allen - 29 Jun, 2018 - Comments: 0

M&A Siemens acquired Austemper Design Systems, which provides tools for functional safety and safety-critical designs. Founded in 2015, Texas-based Austemper adds state-of-the-art safety analysis, auto-correction and fault simulation technology to address random hardware faults, as well as correct and harden vulnerable areas, subsequently performing fault simulation to ensure the design is... » read more

Abstraction Aging
By Brian Bailey - 28 Jun, 2018 - Comments: 1

During the course of doing interviews for my article on system simulation and abstraction, I spoke to several people who, just like myself, had started their career pushing abstraction. At the time, we were all frustrated that the industry didn't move fast enough. The advantages of abstraction appeared to be so clear. Everyone developed slides showing that the cost to fix bugs increased the fur... » read more

Adding NoCs To FPGA SoCs
By Ann Mutschler - 28 Jun, 2018 - Comments: 0

FPGA SoCs straddle the line between flexibility and performance by combining elements of both FPGAs and ASICs. But as they find a home in more safety- and mission-critical markets, they also are facing some of the same issues as standard SoCs, including the ability to move larger and larger amounts of data quickly throughout an increasingly complex device, and the difficulty in verifying and de... » read more

Searching For A System Abstraction
By Brian Bailey - 28 Jun, 2018 - Comments: 3

Without abstraction, advances in semiconductor design would have stalled decades ago and circuits would remain about the same size as analog blocks. No new abstractions have emerged since the 1990s that have found widespread adoption. The slack was taken up by IP and reuse, but IP blocks are becoming larger and more complex. Verification by isolation is no longer a viable strategy at the system... » read more

DAC 2018: System Design, Cloud And Machine Learning
By Frank Schirrmeister - 28 Jun, 2018 - Comments: 0

This marks the 10th DAC that I have covered as a blogger. At DAC 2008 in Anaheim, the industry had just come together behind the SystemC TLM 2.0 standard to enable virtual platforms, finally getting to model interoperability. System design is the common thread that is also present in this year’s DAC in 2018 in San Francisco. But a lot has changed. Big data analytics, artificial intelligence a... » read more

Tuesday At DAC 2018
By Brian Bailey - 27 Jun, 2018 - Comments: 0

The morning starts with the Accellera Breakfast. Accellera has made some significant progress this year and we can expect to hear about the approval of the Portable Stimulus 1.0 specification later in the conference as well as the initial release of SystemC CCI as well as a proposal for the creation of an IP Security Assurance Working Group, which will discuss standards development to address s... » read more

Blog Review: June 27
By Jesse Allen - 27 Jun, 2018 - Comments: 0

Applied Materials' Sundeep Bajikar argues that to realize the full potential of AI, new computing architectures are necessary, otherwise AI will quickly become unaffordable. Synopsys' Iain Singleton considers why it may not always be necessary to start at the reset state during formal verification and how to use abstractions to get a head start on bug hunting. Cadence's Meera Collier look... » read more

Monday At DAC 2018
By Brian Bailey - 26 Jun, 2018 - Comments: 0

DAC #55 started with rumors flying. Will this be the last DAC as we know it? Is there a huge chasm forming between academia and the industry? Will DAC be able to make it in Las Vegas where there is no local interest? Of course, those who have been in the industry know that this kind of speculation happens every few years, and in the 80s, Las Vegas was a very popular location for DAC. There was ... » read more

Defining Edge Memory Requirements
By Ann Mutschler - 20 Jun, 2018 - Comments: 0

Defining edge computing memory requirements is a growing problem for chipmakers vying for a piece of this market, because it varies by platform, by application, and even by use case. Edge computing plays a role in artificial intelligence, automotive, IoT, data centers, as well as wearables, and each has significantly different memory requirements. So it's important to have memory requirement... » read more

Blog Review: June 20
By Jesse Allen - 20 Jun, 2018 - Comments: 0

Mentor's Randy Allen digs into OpenACC, a collection of directives and routines to help a compiler uncover and schedule parallelism, plus an examination of the GCC implementation's performance. Cadence's Paul McLellan takes a look at the shifting opinions on FD-SOI vs. finFET as Dan Hutcheson of VLSI Research finds most see the two as complementary technologies in his latest survey. Synop... » read more

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