tag: Cadence

Week In Review: Design, Low Power
By Jesse Allen - 26 Jul, 2019 - Comments: 0

CEVA acquired the Hillcrest Labs business from InterDigital. Hillcrest Labs supplies software and components for sensor processing in consumer and IoT devices. Hillcrest Labs' MotionEngine sensor processing software already runs on CEVA DSPs (as well as ARM and RISC-V cores) and enables high accuracy 6-axis and 9-axis sensor fusion, dynamic sensor calibration, and application specific features ... » read more

Verification Requirements For 5G To Enable A Perfect Storm Of New Applications
By Frank Schirrmeister - 25 Jul, 2019 - Comments: 0

In my role as product management lead, to understand drivers for verification requirements and semiconductor markets I often exchange thoughts with customers what they think the next “killer app” would be. Ten years back, the drivers seemed pretty clear and segmented on a small number of applications, but the outlook today in 2019 is much more diverse. 5G networking seems to be a binding el... » read more

Hardware-Software Co-Design Reappears
By Brian Bailey - 25 Jul, 2019 - Comments: 1

The core concepts in hardware-software co-design are getting another look, nearly two decades after this approach was first introduced and failed to catch on. What's different this time around is the growing complexity and an emphasis on architectural improvements, as well as device scaling, particularly for AI/ML applications. Software is a critical component, and the more tightly integrate... » read more

Power Is Limiting Machine Learning Deployments
By Brian Bailey - 25 Jul, 2019 - Comments: 3

The total amount of power consumed for machine learning tasks is staggering. Until a few years ago we did not have computers powerful enough to run many of the algorithms, but the repurposing of the GPU gave the industry the horsepower that it needed. The problem is that the GPU is not well suited to the task, and most of the power consumed is waste. While machine learning has provided many ... » read more

Hybrid Emulation Takes Center Stage
By Ann Mutschler - 25 Jul, 2019 - Comments: 0

From mobile to networking to AI applications, system complexity shows no sign of slowing. These designs, which may contain multiple billion gates, must be validated, verified and tested, and it’s no longer possible to just throw the whole thing in a hardware emulator. For some time, emulation, FPGA-based prototyping, and virtual environments such as simulators have given design and verific... » read more

How To Optimize Verification
By Brian Bailey - 25 Jul, 2019 - Comments: 0

The rate of improvement in verification tools and methodologies has been nothing short of staggering, but that has created new kinds of problems for verification teams. Over the past 20 years, verification has transformed from a single language (Verilog) and tool (simulator) to utilizing many languages (testbench languages, assertion languages, coverage languages, constraint languages), many... » read more

Blog Review: July 24
By Jesse Allen - 24 Jul, 2019 - Comments: 0

Synopsys' Taylor Armerding notes that while two Florida cities may have saved taxpayers millions by paying ransomware demands, doing so is likely setting up a ransomware tsunami that threatens other municipalities. In a video, Cadence's Jacek Duda digs into what's going on with the upcoming USB4 standard and what will change compared to USB 3.x. Mentor's Colin Walls shares a few embedded ... » read more

Using Memory Differently To Boost Speed
By Ed Sperling - 22 Jul, 2019 - Comments: 2

Boosting memory performance to handle a rising flood of data is driving chipmakers to explore new memory types and different ways of using existing memory, but it also is creating some complex new challenges. For most of the semiconductor design industry, memory has been a non-issue for the past couple of decades. The main concerns were price and size, but memory makers have been more than a... » read more

Partitioning Drives Architectural Considerations
By Ann Mutschler - 19 Jul, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss partitioning with Raymond Nijssen, vice president of system engineering at Achronix; Andy Ladd, CEO at Baum; Dave Kelf, chief marketing officer at Breker; Rod Metcalfe, product management group director in the Digital & Signoff Group at Cadence; Mark Olen, product marketing group manager at Mentor, a Siemens Business; Tom Anderson, technical mar... » read more

Week In Review: Design, Low Power
By Jesse Allen - 19 Jul, 2019 - Comments: 0

Tools & IP Arm has a new access and licensing model for its IP. Flexible Access allows SoC design teams to initiate projects before they license IP by paying a yearly fee for immediate access to a broad portfolio of technology, then paying a license fee only when they commit to manufacturing, followed by royalties for each unit shipped. IP available through Arm Flexible Access includes the... » read more

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