tag: Cadence

Blog Review: July 17
By Jesse Allen - 17 Jul, 2019 - Comments: 0

Mentor's John McMillan takes a look at the three general classes that have been established by IPC-2221B to reflect progressive increases in sophistication, functional performance requirements, and testing/inspection frequency for PCBs. Synopsys' Dinesh Siwal and Thenmozhy Kaliyamurthy point out the new features and improvements in DisplayPort 2.0, including greater speeds, better power effi... » read more

Breaking Down The Debug Process
By Brian Bailey - 17 Jul, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss debugging complex SoCs with Randy Fish, vice president of strategic accounts and partnerships for UltraSoC; Larry Melling, product management director for Cadence; Mark Olen, senior product marketing manager for Mentor, a Siemens Business; and Dominik Strasser, vice president of engineering for OneSpin Solutions. Part one can be found here. What fol... » read more

Low-Power Design Becomes Even More Complex
By Ann Mutschler - 16 Jul, 2019 - Comments: 0

Throughout the SoC design flow, there has been a tremendous amount of research done to ease the pain of managing a long list of power-related issues. And while headway has been made, the addition of new application areas such as AI/ML/DL, automotive and IoT has raised as many new problems as have been solved. The challenges are particularly acute at leading-edge nodes where devices are power... » read more

Will In-Memory Processing Work?
By Brian Bailey - 16 Jul, 2019 - Comments: 1

The cost associated with moving data in and out of memory is becoming prohibitive, both in terms of performance and power, and it is being made worse by the data locality in algorithms, which limits the effectiveness of cache. The result is the first serious assault on the von Neumann architecture, which for a computer was simple, scalable and modular. It separated the notion of a computatio... » read more

Blog Review: July 10
By Jesse Allen - 10 Jul, 2019 - Comments: 0

Synopsys' Eric Huang takes a look at how backward compatibility with USB 2.0 is provided when the IO voltages of new nodes can't support 3.3V signaling and how eUSB2 can boost the signal and provide support for external or legacy peripherals. In a video, Mentor Colin Walls explains endianness in embedded systems with a look at what it is, when it matters, and how to accommodate it in code. ... » read more

Silicon Photonics Begins To Make Inroads
By Kevin Fogarty and Ed Sperling - 09 Jul, 2019 - Comments: 1

Integrating photons and electrons on the same die is still a long way off, but advances in packaging and improvements in silicon photonics are making it possible to use optical communication for a variety of new applications. Utilizing light-based communication between chips, or in self-contained modules, ultimately could have a big impact on chip design. Photons moving through waveguides ar... » read more

5G OTA Test Not Ready For Production
By Kevin Fogarty - 09 Jul, 2019 - Comments: 0

5G is poised to dominate the wireless world, but over-the-air (OTA) testing of 5G beamforming antennas is still not ready for volume production. Beamforming is a critical element in the millimeter wave version of 5G, because of the limitations of ultra-high-frequency signals. Unlike 4G and its predecessors, millimeter wave technology will not penetrate objects, so signals need to be directed... » read more

HW/SW Design At The Intelligent Edge
By Ann Mutschler - 08 Jul, 2019 - Comments: 0

Adding intelligence to the edge is a lot more difficult than it might first appear, because it requires an understanding of what gets processed where based on assumptions about what the edge actually will look like over time. What exactly falls under the heading of Intelligent Edge varies from one person to the next, but all agree it goes well beyond yesterday’s simple sensor-based IoT dev... » read more

Week In Review: Design, Low Power
By Jesse Allen - 05 Jul, 2019 - Comments: 0

Si2's Unified Power Model has been approved as IEEE 2416-2019, a new Standard for Power Modeling to Enable System Level Analysis, which complements UPF/IEEE 1801-2018. UPM/IEEE 2416-2019 provides a set of power modeling semantics enabling system designers to model entire systems with flexibility. It supports power modeling from abstract design description to gate level implementation, providing... » read more

Blog Review: July 3
By Jesse Allen - 03 Jul, 2019 - Comments: 0

Cadence's Paul McLellan digs into 5G with a two-part post explaining the basics of the technology, what makes it so different from 4G, and the challenges ahead including the limitations of mmWave. Synopsys' Vikramjeet Bamel and Pankaj Sharma note the features that make GDDR6 a dominant memory in the high performance segment and allowing it to expand beyond graphics to automotive, AI, and AR/... » read more

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