Week In Review: Design, Low Power

Tools & IP
Arm has a new access and licensing model for its IP. Flexible Access allows SoC design teams to initiate projects before they license IP by paying a yearly fee for immediate access to a broad portfolio of technology, then paying a license fee only when they commit to manufacturing, followed by royalties for each unit shipped. IP available through Arm Flexible Access includes the majority of processors within the  Cortex-A, -R and -M families as well as TrustZone and CryptoCell security IP, select Mali GPUs, system IP, and tools and models for SoC design and early software development.

Cadence debuted a Portable Test and Stimulus Specification 1.0-compliant source code form of the Perspec System Methodology Library and PSS methodology documentation. The PSS methodology library enables Perspec System Verifier customers to access PSS source code for any of the SML functions to develop models. Additionally, the library in source form along with the methodology documentation will be provided to non-Perspec users to help promote the adoption of the PSS. The new PSS methodology and library was checked by AMIQ using its DVT Eclipse IDE to confirm the new library is PSS Language Reference Manual compliant.

Silexica released the latest version of its SLX development tools. SLX FPGA features improvements to prepare and optimize C/C++ code for High Level Synthesis in the Xilinx Vivado HLS design flow, including code transformations for synthesizability, hardware aware parallelism extraction, and a code refactoring wizard. SLX C/C++ features improved multi-process analysis including support for the use of named POSIX semaphores, extended graphical visualization, user-defined thread names, and performance estimation for each processor.

Synopsys and Ixia, a Keysight Business, are teaming up on system validation of complex networking SoCs by integrating Synopsys’ ZeBu emulation system with Ixia’s IxVerify virtual network tester. The combined ZeBu Virtual Network Tester Solution aims to replace traditional in-circuit emulation for networking SoCs and provide a full-featured protocol testing solution for pre- and post-silicon use.

SmartDV announced Verification IP for DisplayPort 2.0. The VIP includes a configurable bus functional model (BFM), protocol monitor and library of integrated protocol checks, and supports all major verification languages and methodologies, including OVM, UVM and SystemC. DisplayPort 2.0 allows for a max payload of 77.37 Gbps and uses the Thunderbolt 3 PHY layer.

Arasan Chip Systems uncorked MIPI D-PHY IP supporting speeds of up to 2.5 Gbps for TSMC 22nm SoC designs. Compliant to MIPI D-PHY Spec v1.2, the IP reuses multiple blocks previous silicon proven 28nm technology to reduce risk while being optimized to leverage the TSMC 22nm technology node for reduction in area and power. It is integrated with the company’s CSI Tx, CSI Rx, DSI Tx and DSI Rx IP.

Alphawave IP debuted its PipeCORE PCIe Gen1-5 PHY available on TSMC’s 7nm process technology. The IP can also demonstrate 64Gbps PAM4 rates for early PCI-Express Gen6 adopters. PipeCORE is highly configurable and available in one, two, four, eight and sixteen lane configurations. It consumes less than 200mW of power at 32Gbps.

Deals
A collaboration between UltraSoC, the University of Southampton, the University of Coventry, and cybersecurity specialist consultancy Copper Horse secured £2m ($2.51m) in support from the Innovate UK government agency in developing an on-chip monitoring solution to identify security and safety issues in connected and autonomous vehicles. Along with the monitoring solution, the group will develop a testbed demonstrator representing a full-scale automotive functional architecture and model cybersecurity scenarios to test the robustness of the project’s output.

Innovium adopted Cadence’s Innovus Implementation System for its 16nm TERALYNX 12.8Tbps ethernet switches for data centers. Innovium cited the tool as helping meet PPA goals and improve overall engineering productivity.

Synopsys will continue working on DARPA’s Posh Open Source Hardware (POSH) program focusing on analog/mixed-signal (AMS) emulation as part of the Electronics Resurgence Initiative (ERI). The company will work with Lockheed Martin in the next phase of the program to provide systems and security expertise.

NSITEXE selected Cadence’s digital design full flow for its high-efficiency, high-quality data flow processor (DFP) IP for automotive and industrial applications. NSITEXE cited a reduction in turnaround time by 75% and improvement in power by 8.5%, performance by 35% and reduced area by 3.5% when compared with its previous competitive solution.