tag: Cadence

I Say ‘High’ [Performance], You Say ‘Low’ [Power]
By Vinay Patwardhan - 10 Aug, 2017 - Comments: 0

“…You say ‘why’, and I say ‘I don’t know…’” Actually, I do know. Everybody loves a high-performance product. Even just hearing that a product is high-performance sets higher expectations than if the product is simply described as “fast” or “powerful.” When it comes to SoC design, “high-performance” refers to a set of designs that run at very high clock freque... » read more

Is Design Innovation Slowing?
By Brian Bailey - 10 Aug, 2017 - Comments: 0

Paul Teich, principal analyst for Tirias Research, gave a provocative talk at the recent DAC conference entitled, "Is Integration Leaving Less Room for Design Innovation?" The answer isn't as simple as the question might suggest. "Integration used to be a driver for increasing the functionality of silicon," Teich said. "Increasingly, it will be used to incorporate more features of an entire ... » read more

IP Challenges Ahead
By Brian Bailey - 10 Aug, 2017 - Comments: 0

The revenue from semiconductor [getkc id="43" kc_name="IP"] has risen steadily to become the largest segment of the EDA industry. Industry forecasts expect it to keep growing at a CAGR of more than 10% for the next decade. Part one of this article examined the possibility those forecasts are wrong and that large semiconductor companies are likely to start bringing IP development back in hous... » read more

Modeling Of The Electrical Performance Of The Power And Ground Supply For A PC Microprocessor On A Card
By Cadence - 09 Aug, 2017 - Comments: 0

The electrical characteristics of the power and ground supply of a PC microprocessor packaged in a Ball Grid Array (BGA) package mounted on a card are studied by dynamic electromagnetic field analysis. The effects of decoupling capacitors of different types and at different locations are investigated to achieve the objectives of low power and ground impedance and no or insignificant resonances ... » read more

Blog Review: Aug. 9
By Jesse Allen - 09 Aug, 2017 - Comments: 0

Cadence's Paul McLellan digs into a recently discovered vulnerability in the Broadcom Wi-Fi chip used in many smartphones and why it should be a wakeup call for SoC designers. Mentor's Craig Armenti considers whether work-in-process design data management is an asset or a liability. Synopsys' Thomas M. Tuerke notes that in code, as in medicine, proper hygiene is should be treated as a con... » read more

The Rising Value Of Data
By Ed Sperling - 09 Aug, 2017 - Comments: 0

The volume of data being generated by a spectrum of devices continues to skyrocket. Now the question is what can be done with that data. By Cisco's estimates, traffic on the Internet will be 3.3 zetabytes per year by 2021, up from 1.2 zetabytes in 2016. And if that isn't enough, the flow of data isn't consistent. Traffic on the busiest 60-minute period in a day increased 51% in 2016, compare... » read more

IP Business Changing As Markets Shift
By Ed Sperling - 03 Aug, 2017 - Comments: 0

Semiconductor Engineering sat down to discuss IP protection, tracking and reuse with Srinath Anantharaman, CEO of [getentity id="22203" e_name="ClioSoft"]; and Jeff Galloway, CTO of Silicon Creations; Marc Greenberg, group director of product marketing for [getentity id="22032" e_name="Cadence"]'s IP Group; and John Koeter, vice president of marketing for [getentity id="22035" e_name="Synopsys"... » read more

Blog Review: Aug. 2
By Jesse Allen - 02 Aug, 2017 - Comments: 0

In a video, Cadence's Marc Greenberg describes the post-package repair capability in LPDDR4 and why it's important for future LP/DDR5 memories. Synopsys' Kiran Vittal looks at formal, machine learning, and when computers beat humans at games. Mentor's Matt Knowles digs into how cell-aware diagnosis works and why it can find tricky finFET defects. ARM's Freddi Jeffries digs into why com... » read more

CCIX Enables Machine Learning
By Brian Bailey - 31 Jul, 2017 - Comments: 5

It takes a lot of technology to enable something like machine learning, and not all of it is as glamorous as neural network architectures and algorithms. Several levels below that is the actual hardware on which these run, and that brings us into the even less sexy world of interfaces. One such interface, the Cache Coherent Interconnect for Accelerators (CCIX), pronounced C6, aims to make th... » read more

The Week In Review: Design
By Jesse Allen - 28 Jul, 2017 - Comments: 0

IP Synopsys unveiled High Bandwidth Memory 2 (HBM2) IP. The package includes PHY, controller and verification IP and supports data rates up to 2400Mb/s, 20% faster than the JEDEC standard specification. The controller supports pseudo-channel operation in either lock step or memory interleaved mode, and the PHY offers four trained power management states and fast frequency switching. Cadence... » read more

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