tag: Cadence

Does Hardware/Software Verification Have To Be Broad And Deep? Check Out DVCon 2017
By Frank Schirrmeister - 23 Feb, 2017 - Comments: 0

DVCon 2017 is upon us next week and even though it is called the “Design and Verification” conference, it is rising more and more to the system level. One of the aspects of interest is how verification seems to simultaneously become broader—covering more aspects to verify like software, power and performance—while also becoming more deep when it comes to application domains and their sp... » read more

Massive SoC Designs Open Doors To New Era In Simulation
By Cadence - 22 Feb, 2017 - Comments: 0

As system-on-chip (SoC) designs have grown in size, simulation technologies have had to evolve dramatically to keep pace. We’re now at an inflection point where both speed and capacity are essential and new simulation technologies are needed to meet the demands. In this paper, we’ll discuss how simulation has evolved and examine how new technologies such as the Cadence RocketSimTM Parallel ... » read more

Blog Review: Feb. 22
By Jesse Allen - 22 Feb, 2017 - Comments: 0

Mentor's Brian Derrick digs into the state of the electric vehicle industry and whether established OEMs will be able to make the changes required to meet new consumer demands. Cadence's Paul McLellan listens in on how to greatly improve the efficiency of machine learning, without using custom hardware, in a talk by Stanford's Kunle Olukotun. Synopsys' Robert Vamosi warns not to overlook ... » read more

Blog Review: Feb. 15
By Jesse Allen - 15 Feb, 2017 - Comments: 0

Mentor's Jean-Marie Brunet looks at factors driving the growth of hardware emulation for SoCs. Cadence's Dave Pursley asserts that the role of hardware developers is about to change for the better. Synopsys' Robert Vamosi says that major software vulnerabilities are becoming less frequent, in spite of hype surrounding named bugs. ARM's Rhonda Dirvin discusses the release of the OpenFog... » read more

Test More Complex For Cars, IoT
By Ann Mutschler - 15 Feb, 2017 - Comments: 0

With increasing focus on safety-critical semiconductors—driven by ADAS, IoT, and security—functional safety concerns are going through the roof. Engineering teams are scrambling to determine how to conduct better in-field or online testing because test no longer can be an afterthought. This has been a common theme across the automotive ecosystem for the past few years, and as the automot... » read more

New Memories And Architectures Ahead
By Brian Bailey - 13 Feb, 2017 - Comments: 4

Memory dominates many SoCs, and it is rare to hear that a design contains too much memory. However, memories consume a significant percentage of system power, and while this may not be a critical problem for many systems, it is a bigger issue for Internet of Things ([getkc id="76" kc_name="IoT"]) edge devices where total energy consumption is very important. Memory demands are changing in al... » read more

Devices Threatened By Analog Content?
By Brian Bailey - 09 Feb, 2017 - Comments: 0

As the amount of analog content in connected devices explodes, ensuring that the analog portion works properly has taken on a new level of urgency. Analog circuitry is required for interpreting the physical world and for moving data to other parts of the system, while digital circuitry is the fastest way to process it. So a sensor that gives a faulty reading in a car moving at high speed or ... » read more

What Can Be Cut From A Design?
By Ann Mutschler - 09 Feb, 2017 - Comments: 0

A long-standing approach of throwing everything into a chip increasingly is being replaced by a focus on what can be left out it. This shift is happening at every level, from the initial design to implementation. After years of trying to fill every square nanometer of real estate on a piece of silicon with memory and logic, doubling the number of [getkc id="26" kc_name="transistors"] from on... » read more

Blog Review: Feb. 8
By Jesse Allen - 08 Feb, 2017 - Comments: 0

Mentor's Craig Armenti looks at some of the challenges involved with multi-board PCB or system design. Cadence's Paul McLellan highlights a presentation by Igor Keller on the state of the art in static timing analysis. Synopsys' Eric Huang has some ideas for USB interoperability testing. Intel's Ron Wilson delves into the current state of 5G, and why perspectives on that differ. Ans... » read more

Chip-Package-Board Issues Grow
By Ann Mutschler - 06 Feb, 2017 - Comments: 0

As systems migrate from a single die in a single package on a board, to multiple dies with multiple packaging options and multiple PCB form factors, it is becoming critical to move system planning, assembly, and optimization much earlier in the design-through-manufacturing flow. This is easier said than done. Multiple tools and operating systems are now used at each phase of the flow, partic... » read more

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