tag: Cadence

Top 7 Verification Trends For 2017—Changes In The Game Of Ecosystems
By Frank Schirrmeister - 22 Dec, 2016 - Comments: 0

As the year 2016 comes to a close, how did my predictions from last year hold up to reality? They were all about horizontal and vertical integration. Spoiler alert—they almost all have moved closer to reality. Going forward into 2017, some of the trends will intensify, but the most interesting trend to watch will be how the game of ecosystems in the areas of mobile, server, and intelligent sy... » read more

CEO Outlook: Chip Design 2017
By Ed Sperling - 22 Dec, 2016 - Comments: 0

After two consecutive flat to slightly down years, the semiconductor industry is poised for growth in 2017. Cowan this month predicted 4.7% growth in semiconductor sales in 2017, while World Semiconductor Trade Statistics (WSTS) put that figure at 3.3%. And last month, International Business Strategies (IBS) pegged the number at 4.6%, according to statistics compiled by the Global Semiconduc... » read more

What’s Missing In Advanced Packaging
By Ann Mutschler - 22 Dec, 2016 - Comments: 0

Even though Moore's Law is running out of steam, there is still a need to increase functional density. Increasingly, this is being done with heterogeneous integration at the package or module level. This is proving harder than it looks. At this point there are no standardized methodologies, and tools often are retrofitted versions of existing tools that don't take into account the challenges... » read more

Tools For Heterogeneous System Development
By Brian Bailey - 22 Dec, 2016 - Comments: 1

System architects look to both heterogeneous and homogeneous computing when there are no other options available, but the current thinking is that a system-level software methodology could simplify the design, ease integration of various blocks, and potentially improve performance for less power. While the theory appears sound enough, implementing it has turned out to be harder than expected. ... » read more

Reflecting Back On 2016
By Brian Bailey - 22 Dec, 2016 - Comments: 0

Anyone can make a prediction, and sometimes the more outlandish they are the more they get noticed. But at the end of the year some people hit the mark while others may have been way off. Many people simply make projections based on the current trajectory of trends, while others look for the potential discontinuities that may lie ahead. Semiconductor Engineering examines the projections made... » read more

Blog Review: Dec. 21
By Jesse Allen - 21 Dec, 2016 - Comments: 0

Mentor's Jeff Miller and ARM's Nandan Nayampally contend that it's easier than ever to design custom SoCs. Cadence's Paul McLellan provides a basic primer on silicon photonics, from a presentation by Gilles Lamant. The US Department of Transportation is considering requiring the inclusion of vehicle-to-vehicle communication in new cars, says Synopsys' Robert Vamosi. Applied's Shekar Kr... » read more

DO-254 Explained
By Cadence - 21 Dec, 2016 - Comments: 0

This white paper, the first in a series of DO-254-related white papers, will explore the high-level concepts and activities within the DO-254 Design Assurance Guidance for Airborne Electronic Hardware specification, why they exist, and what they mean. In this paper, we will explore the safety-related concepts of requirements traceability, design assurance levels, the overall DO-254-compliant fl... » read more

The Week In Review: Design
By Jesse Allen - 16 Dec, 2016 - Comments: 0

IP eSilicon launched 14nm FinFET and 28nm planar HBM Gen2 Hardened PHY. It supports up to 256Gbytes/sec bandwidth with 8x128b channels at 2Gbps per I/O, and the integrated I/O supports up to 2Gbps DDR operation across a 4mm interposer channel. The PHY was developed on Samsung 14LPP and TSMC 28HPC technologies. Flex Logix designed a high-performance embedded FPGA IP core for TSMC 16FF+ and... » read more

Blog Review: Dec. 14
By Jesse Allen - 14 Dec, 2016 - Comments: 0

What are the technology options for 5nm? Cadence's Paul McLellan highlights an IEDM presentation by An Steegen of Imec. Synopsys' Michael Posner suggests we may not have to live with USB Type-C dongles for very long. Mentor's Craig Armenti presents some of the fundamental best practices and guidelines for rigid-flex PCB design. NXP's Joe Byrne digs into the Mirai botnet attack, arguing... » read more

Overcoming The Limits Of Scaling
By Ed Sperling - 14 Dec, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss the increasing reliance on architectural choices for improvements in power, performance and area, with [getperson id="11425" comment=" Sundari Mitra"], CEO of [getentity id="22535" comment="NetSpeed Systems"]; Charlie Janac, chairman and CEO of [getentity id="22674" e_name="Arteris"]; [getperson id="11032" comment="Simon Davidmann"] CEO of [getentit... » read more

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