tag: Cadence

Formal’s Roadmap
By Brian Bailey - 12 Dec, 2016 - Comments: 0

Formal verification has come a long way in the past five years as it focused on narrow tasks within the verification flow. Semiconductor Engineering sat down to discuss that progress, and the future of formal technologies, with [getperson id="11306" comment="Raik Brinkmann"], president and CEO of [getentity id="22395" e_name="OneSpin Solutions"]; Harry Foster, chief verification scientist at [g... » read more

Embedded Software Verification Issues Grow
By Ann Mutschler - 08 Dec, 2016 - Comments: 0

Embedded software is becoming more critical in managing the power and performance of complex designs, but so far there is no consensus about the best way to approach it—and that's creating problems. Even with safety-critical standards such as DO-178C for aerospace and [gettech id="31076" comment="ISO 26262"] for automotive, different groups of tool providers approach software from differen... » read more

Tuning Heterogeneous SoCs
By Brian Bailey - 08 Dec, 2016 - Comments: 0

It's one thing to pack multiple processor cores into a design, but it is much more difficult to ensure the hardware matches the software's requirements, or that the software optimally uses the hardware. Both the hardware and software teams are now facing these issues, and there are few tools to help them fully understand the problems or to provide solutions. Design teams continue to add more... » read more

Verification Of Low-Power Designs With Portable Stimulus
By Tom Anderson - 08 Dec, 2016 - Comments: 0

In a recent blog post, Steve Carlson talked about the use of software-driven tests to support concurrent power and performance analysis. Generation of software-driven tests is one of the key technologies that will be enabled by the upcoming standard from Accellera's Portable Stimulus Working Group (PSWG). Portable stimulus spans functional verification as well as performance validation, so PSWG... » read more

Analog’s Rising Status
By Ann Mutschler - 08 Dec, 2016 - Comments: 1

As more sensors and actuators are added into electronic devices, pressure is growing to more seamlessly move data seamlessly back and forth between analog and digital circuitry. [getkc id="37" kc_name="Analog"] and digital always have fit rather uncomfortably together, and that discomfort has grown as [getkc id="81" kc_name="SoCs"] are built using smaller feature sizes. While digital transis... » read more

Reflecting Back on 2016: Markets
By Brian Bailey - 08 Dec, 2016 - Comments: 0

Anyone can make a prediction, and sometimes the more outlandish they are the more they get noticed. But at the end of the year some people hit the mark while others may have been way off. Many people simply make projections based on the current trajectory of trends, while others look for the potential discontinuities that may lie ahead. Semiconductor Engineering examines the projections made... » read more

How High-Level Synthesis Was Used to Develop An Image-Processing IP Design From C++ Source Code
By Cadence - 07 Dec, 2016 - Comments: 0

Imagine working long and hard on a design, only to learn that you need to add new (and more complex) functionality a few months before your targeted tapeout. How can you deliver the performance and capabilities expected in the same timeframe? For Bosch, high-level synthesis (HLS) provided the solution. In this paper, we will discuss how HLS technology enabled the team to meet an aggressive sche... » read more

Timing Closure Issues Resurface
By Ed Sperling - 07 Dec, 2016 - Comments: 1

Timing closure has resurfaced as a major challenge at 10nm and 7nm due to more features and power modes, increased process variation and other manufacturing-related issues. While timing-related problems are roughly correlated to rising complexity in semiconductors, they tend to generate problems in waves—about once per decade. In SoCs, timing closure problems have spawned entire methodolog... » read more

Blog Review: Dec. 7
By Jesse Allen - 07 Dec, 2016 - Comments: 0

Mentor's Harry Foster looks at verification results findings in terms of schedules, number of required spins, and classification of functional bugs, in the latest installment of the Wilson Research Group verification study. Cadence's Paul McLellan provides an overview of the portable stimulus standard currently being worked on at Accellera. Synopsys' Anika Malhotra checks out JESD204B, a ... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 02 Dec, 2016 - Comments: 0

Manufacturing There are more changes at SEMI. SEMI has named David Anderson as president of the SEMI Americas region. Most recently, Anderson was chief executive and chairman of Novati, a specialty manufacturing fab. He replaces Karen Savala, who was president of the SEMI Americas region for six years. In an e-mail, Savala confirmed she left SEMI in October. Meanwhile, in October, SEMI an... » read more

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