tag: Cadence

Enabling Automotive Design
By Ann Mutschler - 07 Dec, 2017 - Comments: 0

Falling automotive electronics prices, propelled by advances in chip manufacturing and innovations on the design side, are driving a whole new level of demand across the automotive industry. Innovations that were introduced at the luxury end of the car market over the past couple years already are being implemented in more standard vehicles. The single biggest driver of change in the automo... » read more

Blog Review: Dec. 6
By Jesse Allen - 06 Dec, 2017 - Comments: 0

Synopsys' Eric Huang examines electromagnetic interference, the Bit Error Rate in USB 3.2 and how different transfer types handle errors. Mentor's Nitin Bhagwath points out several things that can cause DDR signals to behave badly, from excessive ringing to stubs in the channel. Cadence's Paul McLellan listens in as Oski CEO Vigyan Singhal explains the basics of assertion-based verificati... » read more

Which Verification Engine? (Part 2)
By Ed Sperling - 06 Dec, 2017 - Comments: 1

Semiconductor Engineering sat down to discuss the state of verification with Jean-Marie Brunet, senior director of marketing for emulation at [getentity id="22017" e_name="Mentor, a Siemens Business"]; Frank Schirrmeister, senior group director for product management at [getentity id="22032" e_name="Cadence"]; Dave Kelf, vice president of marketing at [getentity id="22395" e_name="OneSpin Solut... » read more

Big Challenges, Changes For Debug
By Ann Mutschler - 04 Dec, 2017 - Comments: 1

By Ann Steffora Mutschler & Ed Sperling Debugging a chip always has been difficult, but the problem is getting worse at 7nm and 5nm. The number of corner cases is exploding as complexity rises, and some bugs are not even on anyone's radar until well after devices are already in use by end customers. An estimated 39% of verification engineering time is spent on debugging activities the... » read more

The Week In Review: Design
By Jesse Allen - 01 Dec, 2017 - Comments: 0

Tools Imperas debuted its RISC-V Processor Developer Suite, a set of models, a software simulator, and tools to validate, verify, and provide early estimation of timing performance and power consumption for RISC-V processors. IP Minima Processor revealed its dynamic-margining subsystem IP for near-threshold voltage design. The startup's hardware and software IP works with a CPU or DSP proc... » read more

5 Pitfalls That May Kill The IoT
By Frank Schirrmeister - 30 Nov, 2017 - Comments: 0

A couple of weeks ago I participated in a panel titled “The Road to a Trillion Devices” organized by Brian Fuller at Arm TechCon. His closing question was whether we will get to the projected trillion devices in twenty years. My answer was that we may even get there faster. His opening question was what the pitfalls would be to make it difficult to get to trillion devices in the next twenty... » read more

Prototyping Partitioning Problems
By Ann Mutschler - 30 Nov, 2017 - Comments: 0

Gaps are widening in the prototyping of large, complex chips because the speed and capacity of the FPGA is not keeping pace with rapid rollout pace of advanced ASICs. This is a new twist for a well-established market. Indeed, prototyping with FPGAs is as old as the [gettech id="31071" t_name="FPGAs"] themselves. Even before they were called FPGAs, logic accelerators or LCAs (logic cell ar... » read more

Tech Talk: Verification
By Ed Sperling - 30 Nov, 2017 - Comments: 0

Frank Schirrmeister, Cadence's senior group director for verification platforms, talks about what's changing in verification with 5G, machine learning, greater connectivity, advanced packaging, and the growing need to build security into designs. https://youtu.be/GMF8BkmdJzE » read more

Could Liquid IP Lead To Better Chips?
By Brian Bailey - 30 Nov, 2017 - Comments: 0

Semiconductor Engineering sat down to discuss the benefits that could come from making IP available as abstract blocks instead of RTL implementations with Mark Johnstone, technical director for Electronic Design Automation for [getentity id="22499" e_name="NXP"] Semiconductor; [getperson id="11489" p_name="Drew Wingard"], CTO at [getentity id="22605" e_name="Sonics"]; Bryan Bowyer, director of ... » read more

Three Things You Need To Know To Use The Accellera PSS
By Cadence - 29 Nov, 2017 - Comments: 0

Three primary considerations for adopting the Accellera Portable Stimulus Standard (PSS) are understanding the following: the value and relevance of this standard; the fundamental concepts of PSS modeling, including building blocks, process, and mindset; and PSS portability and how these scenarios can be applied to a specific platform. In this paper, we explore these three topics. To read mo... » read more

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