tag: Cadence

First Silicon At 14nm
By Ed Sperling - 17 Jan, 2013 - Comments: 0

By Ed Sperling The first 14nm test chips are beginning to roll out the door from foundries, and companies are beginning to trumpet their success. But before anyone pops the champagne corks, there are some caveats. First of all, what most people are billing as 14nm chips are actually mostly 20nm. They are readily willing to concede that point, settling on 16nm, but the reality is that it’s... » read more

All Things To All Customers
By Ed Sperling - 17 Jan, 2013 - Comments: 0

By Ann Steffora Mutschler Low-Power High-Performance Engineering recently spoke with Suresh Menon, VP of systems development at Lattice Semiconductor, about the challenges of directing the development of power-sensitive FPGAs from architectural decisions to identifying the target applications. What follows are excerpts of that discussion. LPHP: When you look at the products that Lattic... » read more

What Happened To Statistical Static Timing Analysis?
By Ann Mutschler - 19 Dec, 2012 - Comments: 0

About five years ago if you listened to the marketing messages in the EDA industry, you would have thought it would be impossible to produce chips without statistical static timing analysis (SSTA). Fast forward to now and the industry seems to have put this approach on the back burner. So what happened? “The idea was that if you modeled your design instead of using a corner-based approa... » read more

Adventures In Verification
By Ed Sperling - 19 Dec, 2012 - Comments: 0

By Ed Sperling Design complexity can be almost bit-mapped with verification complexity. There are so many things that need to be verified in a design these days that full coverage has become almost possible to guarantee. That has created a market for tools to help with the verification process—formal, functional, physical—and different methodologies for using those tools. But how to app... » read more

What’s Ahead For System-Level Design
By Ed Sperling - 19 Dec, 2012 - Comments: 0

By Ann Steffora Mutschler Architecting an SoC today is incredibly difficult. When you add in the number of available transistors, the manufacturing effects of smaller nodes, IP and software that must be integrated, among other things, the challenges just keep mounting. Depending on what market segment the SoC will be designed into has a huge impact, as well. “It is impossible to ove... » read more

Experts At The Table: SoC Verification
By Ed Sperling - 19 Dec, 2012 - Comments: 0

By Ed Sperling System-Level Design sat down to discuss the challenges of verification with Frank Schirrmeister, group director for product marketing of the System Development Suite at Cadence; Charles Janac, chairman and CEO of Arteris, Venkat Iyer, CTO of Uniquify; and Adnan Hamid, CEO of Breker Verification Systems. What follows are excerpts of that discussion. SLD: Is the amount of time... » read more

Executive Outlook
By Ed Sperling - 19 Dec, 2012 - Comments: 0

By Ed Sperling The view from the top of companies is a like a high-level of abstraction for viewing the industry. While engineers get caught up in individual projects, or pieces of projects, CEOs and CTOs tend to see things from a much broader perspective. So what do they see as the big issues and developments over the next 12 to 24 months? System-Level Design asked industry leaders that q... » read more

Keeping Pace With Moore’s Law
By Ann Mutschler - 19 Dec, 2012 - Comments: 0

By Ann Steffora Mutschler As the number of transistors doubles with each move to a smaller manufacturing process technology, there are questions as to whether the current cadre of place and route tools will be able to keep in lock step. Have no fear, assured Saleem Haider, senior director of marketing for physical design and DFM at Synopsys. “For the increase in densities that we get with... » read more

TLM-Driven Design And Verification—Time For A Methodology Shift
By Various Writers - 19 Dec, 2012 - Comments: 0

While today’s RTL design and verification flows are a step up from the gate-level flows of two decades ago, RTL flows are straining to meet the demands of most product teams. When designs are sourced and verified at the register transfer level (RTL), IP reuse is difficult, functional verification is lengthy and cumbersome, and architectural decisions cannot be confirmed prior to RTL verificat... » read more

Looking Back At 2012
By Frank Schirrmeister - 17 Dec, 2012 - Comments: 1

By Frank Schirrmeister This my last post in this Blog for this year and it is time to look back at the year and try to see what’s next. How fast time flies became clear in a funny way to me this morning when listening to the “Tagesschau” while showering – the 8pm news I grew up with back in Germany – courtesy of modern video Blog technology. Apparently the parking fines in inner citi... » read more

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