tag: Cadence

Where Does It Hurt?
By Ed Sperling - 27 Sep, 2012 - Comments: 0

By Ed Sperling The IC design industry is feeling a new kind of pain—this one driven by uncertainty over architectural shifts, new ecosystem interactions and new ways to account for costs. As mainstream ICs move from 50/45/40nm to around 32/28/22nm, there are only two choices for design teams—continue shrinking features or stack dies. In many cases, the ultimate solution may be a combina... » read more

Like Oil And Water
By Ed Sperling - 27 Sep, 2012 - Comments: 0

By Ann Steffora Mutschler For years, the promise and allure of a concurrent design methodology included talk of models, high-level synthesis, virtual prototyping and other system-level technologies all peacefully coexisting in a single design methodology. While it sounds like a good idea, the model-based design approach hasn’t mixed well with the virtual prototype approach. And at l... » read more

The Good And Bad Of Models
By Ed Sperling - 27 Sep, 2012 - Comments: 0

By Ann Steffora Mutschler Driven by fierce competition and the fact that socket decisions are made long before silicon is manufactured, semiconductor companies today ship models and virtual prototypes to their OEMs very early in hopes of locking in the socket. Admittedly, this has been happening for some time, but due to complexity and the need for flexibility of models and virtual platf... » read more

On Design Productivity And Cost of Ownership …
By Frank Schirrmeister - 25 Sep, 2012 - Comments: 0

By Frank Schirrmeister Last weekend I spent time with my 7 ½-year-old daughter (the ½ is crucially important at that age) on our tree house project. Well, it is more a tree “deck” so far, which is quite respectable though given that we just started building it in one weekend (as the book I quickly downloaded that evening on the iPad actually recommended). A project like this gives endles... » read more

Power And Performance: GSS Sees SOI Advantages For FinFETs
By Various Writers - 17 Sep, 2012 - Comments: 0

Are FinFETs better on SOI? In a series of papers, high-profile blogs and subsequent media coverage,Gold Standard Simulations (aka GSS) has indicated that, yes, FinFETs should indeed be better on SOI. To those of us not deeply involved in the research world, much of this may seem to come out of nowhere.  But there’s a lot of history here, and in this blog we’ll take a look at what it’s... » read more

The Double Whammy
By Ed Sperling - 13 Sep, 2012 - Comments: 0

By Ann Steffora Mutschler Given that at 40nm and below every [getkc id="81" kc_name="SoC"] has some mixed-signal content, combined with the fact that power awareness is top priority no matter what the target application is, design teams and verification engineers are grappling with tremendous challenges just to get a chip to yield. “For verification engineers and for designers, this is a ... » read more

LP Test Strategies
By Luke Lang - 13 Sep, 2012 - Comments: 0

By Luke Lang Power during test is one area that is often overlooked. In the worst (but easiest to diagnose) case, excessive test power can lead to a smoking chip on the tester. (You don’t need an engineering education to see the problem.) In a better (but more difficult to diagnose) case, excessive test power will cause reduced yield. Let’s look at what causes excessive test power and how ... » read more

Inflection Points Ahead
By Ed Sperling - 23 Aug, 2012 - Comments: 0

By Ed Sperling Engineering challenges have existed at every process node in semiconductor designs, but at 20nm and beyond, engineers and executives on all sides of the industry are talking about inflection points. An inflection point is literally the place where a curve on a graph turns down or up, but in the semiconductor industry it’s usually associated with the point at which a progres... » read more

Dealing With Test More Effectively
By Ed Sperling - 23 Aug, 2012 - Comments: 0

By Ed Sperling Shrinking geometries are starting to have the same effect on test as they are on other parts of an SoC, with the focus shifting from area to leakage, heat, noise, signal integrity, and the impact on overall system performance. The warning that design teams have to consider test much earlier in the design was issued to chipmakers years ago and largely ignored. At 28nm that war... » read more

Experts at the Table: Stacking the Deck
By Ed Sperling - 23 Aug, 2012 - Comments: 0

By Ann Steffora Mutschler System-Level Design sat down to discuss challenges to 3D-IC adoption with Samta Bansal, product marketing for applied silicon realization in strategy and market development at Cadence; Carey Robertson, product marketing director at Mentor Graphics; Karthik Chandrasekar, member of technical staff in IC Design at Altera; and Herb Reiter, president of EDA2ASIC Consulting... » read more

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