tag: Cadence

Week In Review: Auto, Security, Pervasive Computing
By Marie C. Baca - 27 Jan, 2023 - Comments: 0

The U.S. Department of Defense updated the directive that governs the development and fielding of autonomous and semi-autonomous weapon systems. The revisions include an expanded focus on artificial intelligence, and reference to recently-established organizations like the DoD’s Chief Digital and Artificial Intelligence Office. NIST released a new guidance document aimed at helping organi... » read more

Week In Review: Design, Low Power
By Susan Rambo - 27 Jan, 2023 - Comments: 0

Electronic system design (ESD) industry revenue is up 8.9% from $3,458.2 million in Q3 2021 to $3,767.4 million in Q3 2022 according to a report from SEMI’s ESD Alliance. Read our in-depth take on what this means. In an attempt to make a viable reusable DNA biosensor probe, NIST researchers used an extremely low-power FETdeveloped at CEA-LETI to remove noise in their DNA biosensor circuitr... » read more

IEDM: TSMC N3 Details
By Paul McLellan - 26 Jan, 2023 - Comments: 0

I attended IEDM in San Francisco in December. There were two presentations about TSMC's N3 process. This is actually a bit of a misnomer since TSMC has two N3 processes, one simply called N3. The other (the second generation) is called N3E. The two papers were: Critical Process Features Enabling Aggressive Contacted Gate Pitch Scaling for 3nm CMOS Technology and Beyond A 3nm CMOS FinFl... » read more

Power Issues Causing More Respins At 7nm And Below
By Brian Bailey - 26 Jan, 2023 - Comments: 0

Power consumption has been a major design consideration for some time, but it is far from being a solved issue. In fact, an increasing number of designs have a plethora of power-related problems, and those problems are getting worse in new chip designs. Many designs today are power-limited — or perhaps more accurately stated, thermal-limited. A chip only can consume as much power as it is ... » read more

CXL Picks Up Steam In Data Centers
By Marie C. Baca - 26 Jan, 2023 - Comments: 0

CXL is gaining traction inside large data centers as a way of boosting utilization of different compute elements, such as memories and accelerators, while minimizing the need for additional racks of servers. But the standard is being extended and modified so quickly that it is difficult to keep up with all the changes, each of which needs to be verified and validated across a growing swath of h... » read more

What Does 2023 Have In Store For Chip Design?
By Brian Bailey - 26 Jan, 2023 - Comments: 0

Predictions seem to be easier to make during times of stability, but they are no more correct than at any other period. During more turbulent times, fewer people are courageous enough to allow their opinions to be heard. And yet it is often those views that are more well thought through, and even if they turn out not to be true, they often contain some very enlightening ideas. 2022 saw some ... » read more

Fixed-Point And Floating-Point FMCW Radar Signal Processing With Tensilica DSPs
By Cadence - 25 Jan, 2023 - Comments: 0

Automotive Advanced Driver Assistance Systems (ADAS) applications are increasingly demanding radar modules with better capability and performance. These applications require sophisticated radar processing algorithms and powerful Digital Signal Processors (DSPs) to run them. Because these embedded systems have limited power and cost budgets, the DSP’s Instruction Set Architecture (ISA) needs t... » read more

Choosing The Correct High-Bandwidth Memory
By Ann Mutschler - 25 Jan, 2023 - Comments: 0

The number of options for how to build high-performance chips is growing, but the choices for attached memory have barely budged. To achieve maximum performance in automotive, consumer, and hyperscale computing, the choices come down to one or more flavors of DRAM, and the biggest tradeoff is cost versus speed. DRAM remains an essential component in any of these architectures, despite years ... » read more

Blog Review: Jan. 25
By Jesse Allen - 25 Jan, 2023 - Comments: 0

Cadence's Shyam Sharma shares some important design and verification considerations when working with DDR5 SDRAM and DDR5 DIMM-based memory subsystems, including reset and power on initialization, speed bin compliance, and refresh, RFM, and temperature requirements. Siemens EDA's Harry Foster examines trends in adoption of languages and libraries for IC and ASIC design, testbench creation, a... » read more

Week In Review: Design, Low Power
By Jesse Allen - 20 Jan, 2023 - Comments: 0

Worldwide semiconductor revenue increased 1.1% in 2022 to $601.7 billion, up from $595 billion in 2021, according to preliminary results from Gartner. The combined revenue of the top 25 semiconductor vendors increased 2.8% in 2022 and accounted for 77.5% of the market. The memory segment posted a 10% revenue decrease. Analog showed the strongest growth, up 19% from 2021, followed by discretes, ... » read more

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