tag: Cadence

Will Markets For ML Models Materialize?
By Bryon Moyer - 02 Dec, 2021 - Comments: 0

Developers are spending increasing amounts of time and effort in creating machine-learning (ML) models for use in a wide variety of applications. While this will continue as the market matures, at some point some of these efforts might be seen as reinventing models over and over. Will developers of successful models ever have a marketplace in which they can sell those models as IP to other d... » read more

More Than Moore At iMAPS
By Paul McLellan - 02 Dec, 2021 - Comments: 0

San Diego recently hosted the 54th International Symposium on Microelectronics. That's a very generic title, so you should know that it is run by iMAPS, the International Microelectronics Assembly and Packaging Society. Generally, the conference is just known as iMAPS. One of the keynotes was given by Cadence's KT Moore (in person). His presentation was titled "More Moore or More than Moore: a... » read more

Blog Review: Dec. 1
By Jesse Allen - 01 Dec, 2021 - Comments: 0

Synopsys' Mike Gianfagna points to three events that created a fundamental shift in product development that has enabled rapid introduction of a wide range of new products. Siemens' Sagi Reuven considers some key challenges facing the supply chain and the impact on electronics manufacturers, from rising shipping costs to shortages of raw materials and transportation labor. Cadence's Frank... » read more

Missing Interposer Abstractions And Standards
By Brian Bailey - 29 Nov, 2021 - Comments: 0

The design and analysis of an SoC based on an interposer is not for the faint of heart today, but the industry is aware of the challenges and is attempting to solve them. Until that happens, however, it will be a technique that only large companies can deploy because they need to treat everything almost as if it were a single die. The construction of large systems uses techniques, such as ab... » read more

Blog Review: Nov. 24
By Jesse Allen - 24 Nov, 2021 - Comments: 0

Cadence's Paul McLellan introduces the theory and practice of datapath formal verification and explores two use cases of dot-product accumulate systolic design and hashing design. Siemens EDA's Rich Edelman shows that constructing an in-order UVM scoreboard doesn't have to be a difficult or complex task, and certainly simpler than replacing a laptop's keyboard. Synopsys' Gordon Cooper con... » read more

Product Lifecycle Management For Semiconductors
By Brian Bailey - 23 Nov, 2021 - Comments: 1

Product lifecycle management (PLM) and the semiconductor industry have always been separate, but pressure is growing to integrate them. Automotive, IIoT, medical, and other industries see that as the only way to manage many aspects of their business, and as it stands, semiconductors are a large black box in that methodology. The technology space is driven by a mix of top down and bottom-up p... » read more

Advanced Packaging Shifts Design Focus To System Level
By Ann Mutschler - 23 Nov, 2021 - Comments: 0

Growing momentum for advanced packaging is shifting design from a die-centric focus toward integrated systems with multiple die, but it's also straining some EDA tools and methodologies and creating gaps in areas where none existed. These changes are causing churn in unexpected areas. For some chip companies, this has resulted in a slowdown in hiring of ASIC designers and an uptick in new jo... » read more

Towards Decarbonization: Keeping Electronics Energy Consumption In Check
By Frank Schirrmeister - 23 Nov, 2021 - Comments: 0

The International Technology Roadmap for Semiconductors (ITRS) roadmap famously said in 2001 that "cost of design is the greatest threat to the continuation of the semiconductor roadmap." For years, the industry followed the ITRS updates on productivity improvements provided by automating design and hardware to counteract the looming design cost. The discussion on decarbonization has some simil... » read more

Interop Shift Left: Using Pre-Silicon Simulation for Emerging Standards
By Cadence - 22 Nov, 2021 - Comments: 0

The Compute Express Link (CXL) 2.0 specification, released in 2020, accompanies the latest PCI Express (PCIe) 5.0 specification to provide a path to high-bandwidth, cache-coherent, low-latency transport for many high-bandwidth applications such as artificial intelligence, machine learning, and hyperscale applications, with specific use cases in newer memory architectures such as disaggregated a... » read more

Week In Review: Design, Low Power
By Jesse Allen - 19 Nov, 2021 - Comments: 0

Tools Imperas Software released updated simulator and reference models that support the latest RISC-V extensions for Bit Manipulation 1.0.0, Cryptographic (Scalar) 1.0.0, and Vector 1.0, plus Privilege Specification 1.12. They are offered both as freely available, open-source reference models for the RISC-V community as well as commercial products. Ansys' multiphysics signoff solutions were... » read more

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