Cadence Gobbles Up Jasper

By Brian Bailey - 21 Apr, 2014 - Comments: 4

2012 was the year that everyone remembers Synopsys going on an acquisition binge, but 2014 will go down as the year that Cadence Design Systems decided that EDA was worth investing in. Rather than placing investment bets outside of its core competence, Cadence bought Forte in February and now adds Jasper Design Automation to its fold. Jasper started life as Tempus Fugit in 1999 and became Ja... » read more

Blog Review: April 16

By Ed Sperling - 16 Apr, 2014 - Comments: 0

Cadence’s Richard Goering attended a workshop on “extreme” scale design automation, which looked at where else EDA tools can be used—such as intelligent traffic lights. At least there are well-defined use cases. Mentor’s Nazita Saye has compiled five predictions from the 1964 New York World’s Fair that are worth revisiting. Three of them came true. Check out the ones that didn’... » read more

Switching Activity And The Unknown

By Rob Eccles - 10 Apr, 2014 - Comments: 0

Switching activity is essential to measuring power in digital circuits, and it is also important for optimizing digital designs. Power can be static, caused by leakage, or dynamic, caused by switching. Switching activity is crucial because dynamic power is, after all, proportional to the switching activity in the design. Definition Switching activity is the measurement of changes of signal ... » read more

High Level Synthesis: Significant Differences Remain

By Brian Bailey - 09 Apr, 2014 - Comments: 1

In part 1 of this experts series on high-level synthesis (HLS), Semiconductor Engineering sat down with Mike Meredith, vice president of technical marketing at Cadence/Forte Design Systems; Mark Warren, Solutions Group director at Cadence; Thomas Bollaert, vice president of application engineering at Calypto; and Devadas Varma, senior director at Xilinx. The initial part of the discussion looke... » read more

High Level Synthesis Grows Up

By Brian Bailey - 13 Mar, 2014 - Comments: 2

When Semiconductor Engineering proposed this Experts At The Table discussion, which was held at the recently concluded DVCon, [getentity id="22032" e_name="Cadence"] had yet to express its intention to purchase [getentity id="22087" e_name="Forte"]. Little did we know that the stakes in the [gettech id="31015" comment="high-level synthesis"] (HLS) arena were being raised so high. Is this an in... » read more

Reducing And Optimizing Power

By Ann Mutschler - 03 Mar, 2014 - Comments: 0

While power optimization/reduction techniques such as clock gating do help engineering teams improve designs from a power perspective, more can be done. In fact, there are tools and methodologies under development to incorporate power in a more meaningful way. Part of that involves accurately pinpointing what designers should be looking for. “If you look at academia or research that has... » read more

Blog Review: Feb. 19

By Ed Sperling - 19 Feb, 2014 - Comments: 0

Adding a GUI to an RTOS? It may sound counterintuitive, but Mentor’s Colin Walls looks at why and where they’re being used. Cadence’s Richard Goering infuses some humor into signal integrity, which could definitely use it, courtesy of Eric Bogatin and Henny Youngman. When was the last time you saw a signal integrity engineer rolling on the floor in hysterical laughter? Well, there’s ... » read more

With Low-Power Comes Great Responsibility

By Qazi Faheem Ahmed - 14 Feb, 2014 - Comments: 0

Recent trends in the consumer electronics market show a demand for short, slim, and light-weight but powerful devices (with the only exception being displays, which are getting larger). Therefore area, timing, and power have all become “critical” to design; whereas in the past, one was prioritized over the others depending on design requirements. However, power is the dominant factor tod... » read more

Power Reduction Through Sequential Optimization

By Ann Mutschler - 13 Feb, 2014 - Comments: 1

Dealing with power is a multifaceted challenge and is an equal-opportunity problem — everybody can contribute to the solution and at many levels of abstraction. At the architectural or system level, fundamental tradeoffs are done and the engineering team decides how much memory the system needs, what type of processor, what performance, area, power, among other things. Some people may use ... » read more

The Road Ahead For 2014: Tools

By Brian Bailey - 30 Jan, 2014 - Comments: 0

In the third and final part of this predictions series we see the natural conclusion of market shifts that are driving changes in semiconductors, and which in turn drive the tools and IP needed to create those systems. To be expected, the changes fall into a few areas: New tools, techniques and changes required for smaller geometries; A migration to higher-levels of abstraction and the... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: Calypto