Signoff-Compatible CDC

By Ed Sperling - 29 Jul, 2019 - Comments: 2

Tanveer Singh, senior staff consulting applications engineer at Synopsys, explains why netlist clock domain crossing is now an essential complement to RTL CDC, why CDC issues are worse at advanced nodes and in AI chips, and why dealing with CDC effectively is becoming a competitive requirement for performance and low power. » read more

Week In Review: Design, Low Power

By Jesse Allen - 26 Jul, 2019 - Comments: 0

CEVA acquired the Hillcrest Labs business from InterDigital. Hillcrest Labs supplies software and components for sensor processing in consumer and IoT devices. Hillcrest Labs' MotionEngine sensor processing software already runs on CEVA DSPs (as well as ARM and RISC-V cores) and enables high accuracy 6-axis and 9-axis sensor fusion, dynamic sensor calibration, and application specific features ... » read more

FPGA And System Designs Get To Market Faster Leveraging ASIC-Proven Analysis Tools

By Chris Giles - 30 May, 2019 - Comments: 0

Increasing power constraints have resulted in finer-grained partitioning of designs into functional domains that can have clocks disabled or, more drastically, are powered down entirely. Systems are required to adaptively manage clocks to minimize switching power. Performance and area constraints have led to the abandonment of more conservative practices in favor of more aggressive designs; ... » read more

So Many Waivers Hiding Issues

By Brian Bailey - 05 Oct, 2018 - Comments: 0

Semiconductor Engineering sat down to discuss problems associated with domain crossings with Alex Gnusin, design verification technologist for Aldec; Pete Hardee, director, product management for Cadence; Joe Hupcey, product manager and verification product technologist for Mentor, a Siemens Business; Sven Beyer, product manager design verification for OneSpin; and Godwin Maben, applications en... » read more

Domain Crossing Nightmares

By Brian Bailey - 27 Sep, 2018 - Comments: 1

UPF-Aware Clock-Domain Crossing

By Ed Sperling - 29 Aug, 2018 - Comments: 0

Synopsys’ Namit Gupta talks with Semiconductor Engineering about low-power design techniques at the most advanced process nodes, including how to verify the impact of CDC on power at the register transfer level, how to avoid bugs caused by the post-RTL insertion of low-power devices such as isolation, retention and level shifters. https://youtu.be/HwRe9DHLfmg » read more

Debug Issues Grow At New Nodes

By Ann Mutschler - 26 Jul, 2018 - Comments: 0

Debugging and testing chips is becoming more time-consuming, more complicated, and significantly more difficult at advanced nodes as well as in advanced packages. The main problem is that there are so many puzzle pieces, and so many different use cases and demands on those pieces, that it's difficult to keep track of all the changes and potential interactions. Some blocks are "on" sometimes,... » read more

Raising The Bar On Flat CDC Verification With Hierarchical Data Models

By Ashish Hari - 28 Jun, 2018 - Comments: 0

By Ashish Hari, Aditya Vij, and Ping Yeung Traditionally, clock domain crossing (CDC) verification at the SoC level has relied on flat simulation runs. But flat CDC verification has run out of gas. Largely because of the increase in the number of asynchronous clocks in larger, faster, more complex designs. Flat CDC runs are too performance intensive, time-consuming, and result in high noise.... » read more

Manufacturing Bits: June 6

By Mark LaPedus - 06 Jun, 2017 - Comments: 0

Molecular black holes A group of researchers have used an ultra-bright pulse of X-ray light to hit a tiny atom in a molecule, causing the structure to explode and create a “molecular black hole.” The molecular black hole is different than a black hole in space, however. A black hole is a region in space, which has a gravitational field so strong that no matter or light can escape it. ... » read more

Better Code With RTL Linting And CDC Verification

By Sergei Zaychenko - 23 Feb, 2017 - Comments: 0

Automated design rule checking, or linting, has been around in RTL verification for at least a couple decades, yet still many HDL designers completely ignore this simple yet very powerful bug hunting method. Why would a busy designer need to run this annoying warning generator? The hostility against using conventional linting tools is often explained by the enormous amount of output noise, limi... » read more

← Older posts Newer posts →

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.

by Ed Sperling

Defining The Chiplet Socket

The industry may have started with the wrong approach for enabling a third-party chiplet ecosystem, but who will step in and fix it?

by Brian Bailey

tag: CDC

Signoff-Compatible CDC

Week In Review: Design, Low Power

FPGA And System Designs Get To Market Faster Leveraging ASIC-Proven Analysis Tools

So Many Waivers Hiding Issues

Domain Crossing Nightmares

UPF-Aware Clock-Domain Crossing

Debug Issues Grow At New Nodes

Raising The Bar On Flat CDC Verification With Hierarchical Data Models

Manufacturing Bits: June 6

Better Code With RTL Linting And CDC Verification

Trending Articles

NAND Flash Targets 1,000 Layers

Auto Chip Aging Accelerates In Hot Climates

FOPLP Gains Traction in Advanced Semiconductor Packaging

Testing For Thermal Issues Becomes More Difficult

HBM Options Increase As AI Demand Soars

Knowledge Centers
Entities, people and technologies explored