tag: CEA-List

Research Bits: Jan. 23
By Jesse Allen - 23 Jan, 2024 - Comments: 0

Memristor-based Bayesian neural network Researchers from CEA-Leti, CEA-List, and CNRS built a complete memristor-based Bayesian neural network implementation for classifying types of arrhythmia recordings with precise aleatoric and epistemic uncertainty. While Bayesian neural networks are useful for at sensory processing applications based on a small amount of noisy input data because they ... » read more

Chip Industry Week In Review
By The SE Staff - 06 Oct, 2023 - Comments: 0

By Jesse Allen, Liz Allan, and Gregory Haley A potential government shutdown beginning in November would be "massively disruptive" for the Commerce Department as it continues to disburse critical funding featured in the CHIPS Act to boost semiconductor research and development in the U.S., according to Secretary Gina Raimondo. Global semiconductor industry sales totaled $44 billion in Aug... » read more

Technical Paper Round-Up: May 24
By Linda Christensen - 24 May, 2022 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week.   [table id=29 /] Semiconductor Engineering is in the process of building this library of research papers. Please send suggestions (via comments section below) for what else you’d like us to incorporate. If you have research papers you are trying to promote, we will review them to see if they are a ... » read more

Computational SRAM (C-SRAM) Solution Combining In- and Near-Memory Computing Approaches
By Technical Paper Link - 23 May, 2022 - Comments: 0

New academic paper titled "Towards a Truly Integrated Vector Processing Unit for Memory-bound Applications Based on a Cost-competitive Computational SRAM Design Solution", from researchers at Univ. Grenoble Alpes, CEA-LIST. Abstract "This article presents Computational SRAM (C-SRAM) solution combining In- and Near-Memory Computing approaches. It allows performing arithmetic, logic, and co... » read more

Week In Review: Design, Low Power
By Jesse Allen - 23 Jul, 2021 - Comments: 0

Tools Cadence unveiled Cerebrus Intelligent Chip Explorer, a new machine learning-based tool to drive the Cadence RTL-to-signoff implementation flow. The tool aims to use reinforcement learning to find flow solutions that otherwise might not be explored and applies models to future designs. The company says it can improve productivity up to 10X and PPA up to 20% with optimization of the flow f... » read more

Manufacturing Bits: Feb. 16
By Mark LaPedus - 16 Feb, 2021 - Comments: 0

Hybrid bonding consortium for packaging A*STAR’s Institute of Microelectronics (IME) and several companies have formed a new consortium to propel the development of hybrid bonding technology for chip-packaging applications. The group, called the Chip-to-Wafer (C2W) Hybrid Bonding Consortium, includes A*STAR’s IME organization, Applied Materials, ASM Pacific, Capcon, HD MicroSystems, ONT... » read more

Manufacturing Bits: Dec. 29
By Mark LaPedus - 29 Dec, 2020 - Comments: 1

Chiplet-based exascale computers At the recent IEEE International Electron Devices Meeting (IEDM), CEA-Leti presented a paper on a 3D chiplet technology that enables exascale-level computing systems. The United States and other nations are working on exascale supercomputers. Today’s supercomputers are measured in floating point operations per second. The world’s fastest supercomputers c... » read more

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