Inside EUV Resists

By Mark LaPedus - 17 Nov, 2016 - Comments: 3

Andrew Grenville, chief executive of resist maker Inpria, sat down with Semiconductor Engineering to talk about photoresists for extreme ultraviolet (EUV) lithography. What follows are excerpts of that conversation. SE: Photoresists are a critical part of lithography. Resists are light-sensitive materials. They form patterns on a surface when exposed to light. For EUV, they are critical. Wha... » read more

Where Is Next-Gen Lithography?

By Mark LaPedus - 31 Mar, 2016 - Comments: 2

Semiconductor Engineering sat down to discuss lithography and photomask technologies with Greg McIntyre, director of the Advanced Patterning Department at [getentity id="22217" comment="Imec"]; Harry Levinson, senior fellow and senior director of technology research at [getentity id="22819" comment="GlobalFoundries"]; Uday Mitra, vice president and head of strategy and marketing for the Etch Bu... » read more

Pain Points At 7nm

By Ed Sperling - 24 Mar, 2016 - Comments: 3

Early work has begun on 7nm. Process technology has progressed to the point where IP and tools are being qualified. There is still a long way to go. But as companies begin engaging with foundries on this process node—[getentity id="22586" comment="TSMC"] is talking publicly about it, but [getentity id="22846" e_name="Intel"], [getentity id="22819" comment="GlobalFoundries"] and [getentity ... » read more

EUV Resists Move Forward

By Katherine Derbyshire - 23 Mar, 2016 - Comments: 0

Improvements in EUV exposure sources and exposure tools are shifting the industry’s focus to other components of the lithography process. As noted last year, one of the key areas is photoresists. But advanced photoresists face significant challenges, due to the need to balance sensitivity, etch selectivity, and resolution. This year’s SPIE Advanced Lithography conference featured promis... » read more

Where Is Next-Gen Lithography?

By Mark LaPedus - 17 Mar, 2016 - Comments: 4

What’s Really Causing Line-Edge Roughness?

By Katherine Derbyshire - 19 Nov, 2015 - Comments: 0

As previously discussed, shot noise is an important contributor to line edge roughness. However, as the title of one paper on the subject put it, “Do not always blame the photons.” The line edge roughness of a chemically amplified resist ultimately depends on photoacid generation and the deprotection of the resist’s base monomers. Photons absorbed by the resist simply trigger a chain ... » read more

Newer posts →

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.

by Ed Sperling

Defining The Chiplet Socket

The industry may have started with the wrong approach for enabling a third-party chiplet ecosystem, but who will step in and fix it?

by Brian Bailey

tag: chemically amplified resists

Inside EUV Resists

Where Is Next-Gen Lithography?

Pain Points At 7nm

EUV Resists Move Forward

Where Is Next-Gen Lithography?

What’s Really Causing Line-Edge Roughness?

Trending Articles

NAND Flash Targets 1,000 Layers

Testing For Thermal Issues Becomes More Difficult

Auto Chip Aging Accelerates In Hot Climates

Is In-Memory Compute Still Alive?

Baby Steps Toward 3D DRAM

Knowledge Centers
Entities, people and technologies explored