Week In Review: Design, Low Power

By Jesse Allen - 08 Nov, 2019 - Comments: 0

Cadence unveiled a static timing/signal integrity analysis and power integrity analysis tool, Tempus Power Integrity Solution, that integrates the Tempus Timing Signoff and Voltus IC Power Integrity signoff engines. Early use cases demonstrated it correctly identified IR drop errors, avoiding silicon failure prior to tapeout and improving the maximum frequency in silicon by up to 10%. Arasan... » read more

Week In Review: Design, Low Power

By Jesse Allen - 18 Oct, 2019 - Comments: 0

Allegro DVT acquired Amphion Semiconductor, bringing together two developers of video codec IP. Allegro DVT said the merger will make it the first semiconductor IP company to offer commercially available hardware-based, real-time encoder and decoder solutions for the new AV1 video encoding format for SoC implementations, supporting 4K/UHD up to 8K. Based in Belfast, Northern Ireland, Amphion wa... » read more

Week In Review: Design, Low Power

By Jesse Allen - 20 Sep, 2019 - Comments: 0

Tools & IP Synopsys debuted its new DesignWare ARC EV7x Embedded Vision Processor family for machine learning and AI edge applications. The ARC EV7x Vision Processors integrate up to four enhanced vector processing units (VPUs) and an optional Deep Neural Network (DNN) accelerator with up to 14,080 MACs to deliver up to 35 TOPS performance in 16nm FinFET process technologies under typical ... » read more

Week In Review: Design, Low Power

By Jesse Allen - 09 Aug, 2019 - Comments: 0

Synopsys will acquire QTronic GmbH, a provider of simulation, test tools, and services for automotive software and systems development. Based in Germany, QTronic was founded in 2006 and makes a virtual ECU platform as well as a test automation solution with test case generator. Terms of the deal were not disclosed. VeriSilicon uncorked VIP9000, a highly scalable and programmable processor fo... » read more

Are Digital Twins Something For EDA To Pursue?

By Ann Mutschler - 07 Aug, 2019 - Comments: 0

‘Digital Twins’ are one of the new, fashionable key concepts for system developers, but do they fit with EDA? How many different types of engines do these twins run on – abstract simulation, signal-based RTL simulation, emulation, prototyping, actual silicon? What should the use models be called for digital twinning – like reproduction of bugs from silicon in emulation? Or optimizing th... » read more

The Great Test Blur

By Ed Sperling - 06 Aug, 2019 - Comments: 0

As chip design and manufacturing shift left and right, concerns over reliability are suddenly front and center. But figuring out what exactly what causes a chip to malfunction, or at least not meet specs for performance and power, is getting much more difficult. There are several converging trends here, each of which plays an integral role in improving reliability. But how significant a role... » read more

Circuit Aging Becoming A Critical Consideration

By Ann Mutschler - 17 Jun, 2019 - Comments: 5

Circuit aging was considered somebody else's problem when most designs were for chips in consumer applications, but not anymore. Much of this reflects a shift in markets. When most chips were designed for consumer electronics, such as smart phones, designs typically were replaced every couple of years. But with the mobile phone market flattening, and as chips increasingly are used in automot... » read more

Week In Review: Design, Low Power

By Jesse Allen - 14 Jun, 2019 - Comments: 0

M&A Intel will acquire Barefoot Networks, a maker of programmable Ethernet switch silicon and the P4 networking programming language for data centers. Founded in 2013, the Santa Clara-based company has raised $155.4 million in funding. Terms of the deal were not disclosed, but Intel expects the acquisition to be final in the third quarter of this year. Tools & IP Mentor extended it... » read more

Why Chips Are Getting Noisier

By Brian Bailey - 13 Jun, 2019 - Comments: 4

In the past, designers only had to worry about noise for sensitive analog portions of a design. Digital circuitry was immune. But while noise gets worse at newer process nodes, staying at 28nm does not mean that it can be ignored anymore. With Moore's Law slowing, designs have to do more with less. Margins are being squeezed, additional concurrency is added, and attempts are made to opti... » read more

Unveil The Mystery Of Code Coverage In Low-Power Designs: Achieving Power Aware Verification

By Mentor, a Siemens Business - 12 Jun, 2019 - Comments: 0

This paper discusses challenges in code coverage of low-power designs and approaches to overcome those challenges. Also explained is how total coverage results can be visualized in order to achieve verification closure in significantly less time. To read more, click here. » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

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3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

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tag: chip design

Week In Review: Design, Low Power

Week In Review: Design, Low Power

Week In Review: Design, Low Power

Week In Review: Design, Low Power

Are Digital Twins Something For EDA To Pursue?

The Great Test Blur

Circuit Aging Becoming A Critical Consideration

Week In Review: Design, Low Power

Why Chips Are Getting Noisier

Unveil The Mystery Of Code Coverage In Low-Power Designs: Achieving Power Aware Verification