tag: chiplets

How To Make Chiplets A Viable Market
By Paul McLellan - 23 Feb, 2023 - Comments: 0

At the recent Chiplet Summit, there was a panel session on the last afternoon titled "How to Make Chiplets a Viable Market." The panel was moderated by Meta's Ravi Agarwal, and the panelists were (from left to right in the photo): Travis Lanier of Ventana Micro Systems...actually Travis couldn't make it and Ventana was represented by Charles, but I didn't catch his last name Clint Walk... » read more

Dealing With Performance Bottlenecks In SoCs
By Brian Bailey - 23 Feb, 2023 - Comments: 0

A surge in the amount of data that SoCs need to process is bogging down performance, and while the processors themselves can handle that influx, memory and communication bandwidth are straining. The question now is what can be done about it. The gap between memory and CPU bandwidth — the so-called memory wall — is well documented and definitely not a new problem. But it has not gone away... » read more

Chiplets Taking Root As Silicon-Proven Hard IP
By Ann Mutschler - 09 Feb, 2023 - Comments: 0

Chiplets are all the rage today, and for good reason. With the various ways to design a semiconductor-based system today, IP reuse via chiplets appears to be an effective and feasible solution, and a potentially low-cost alternative to shrinking everything to the latest process node. To enable faster time to market, common IP or technology that already has been silicon-proven can be utilized... » read more

Big Changes Ahead For Chip Technology And Industry Dynamics
By Ed Sperling - 08 Feb, 2023 - Comments: 0

Semiconductor Engineering sat down to discuss the impact of customization and advanced packaging, and concerns about reliability and geopolitical rivalries with Martin van den Brink, president and CTO of ASML; Luc Van den Hove, CEO of imec; David Fried, vice president of computational products at Lam Research; and Ankur Gupta, vice president and general manager of the test group and lifecycle s... » read more

Research Bits: Feb. 6
By Jesse Allen - 06 Feb, 2023 - Comments: 0

Pillars for chiplet integration Researchers from the Tokyo Institute of Technology proposed a new chiplet integration technology called Pillar-Suspended Bridge (PSB), which they say is a simpler method of chip-to-chip connection compared to silicon interposers and redistribution layers. In the PSB, only a pillar-shaped metal structure called a "MicroPillar" is interposed at the connection b... » read more

What Does 2023 Have In Store For Chip Design?
By Brian Bailey - 26 Jan, 2023 - Comments: 0

Predictions seem to be easier to make during times of stability, but they are no more correct than at any other period. During more turbulent times, fewer people are courageous enough to allow their opinions to be heard. And yet it is often those views that are more well thought through, and even if they turn out not to be true, they often contain some very enlightening ideas. 2022 saw some ... » read more

An OSAT Perspective On Semiconductor Market Trends
By Vik Chaudhry - 19 Jan, 2023 - Comments: 0

For the semiconductor industry, 2022 was a very interesting year. On one hand, it witnessed shortages in the supply chain. On the other hand, the macro-economic situation turned and demand for several consumer and computing devices plummeted. A trade war with China and ensuing localization of supply chain with passage of CHIPS act took shape in 2022. The auto industry is still recovering from t... » read more

The Path To Known Good Interconnects
By Laura Peters - 19 Jan, 2023 - Comments: 1

Chiplets and heterogenous integration (HI) provide a compelling way to continue delivering improvements in performance, power, area, and cost (PPAC) as Moore’s Law slows, but choosing the best way to connect these devices so they behave in consistent and predictable ways is becoming a challenge as the number of options continues to grow. More possibilities also bring more potential interac... » read more

Looking Inside Of Chips
By Ed Sperling - 10 Jan, 2023 - Comments: 0

Shai Cohen, co-founder and CEO of proteanTecs, sat down with Semiconductor Engineering to talk about how to boost reliability and add resiliency into chips and advanced packaging. What follows are excerpts of that conversation. SE: Several years ago, no one was thinking about on-chip monitoring. What's changed? Cohen: Today it is obvious that a solution is needed for optimizing performanc... » read more

Multi-Die Integration
By Ed Sperling - 04 Jan, 2023 - Comments: 0

Putting multiple heterogeneous chips is the way forward for improved performance and more functionality, but it also brings a host of new challenges around partitioning, layout, and thermal. Michael Posner, senior director for die-to-die connectivity at Synopsys, talks about the advantages of 3D integration, why it’s finally going mainstream, and what’s needed in the EDA tools to make this ... » read more

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