tag: chiplets

Complex Heterogeneous Integration Drives Innovation In Semiconductor Test
By Jeorge Hurtarte - 15 Oct, 2024 - Comments: 0

Heterogeneous integration is driving innovation in the semiconductor industry, but it also introduces more complexity in chip design, which translates to more intricate test requirements. The automated test equipment (ATE) industry is responding, developing and utilizing more sophisticated test equipment capable of handling the diverse functionalities and interfaces needed to test heterogeneous... » read more

Chiplet-Level HI of Polymer-Based Circuits For Fabricating Flexible Electronic-Photonic Integrated Devices
By Technical Paper Link - 09 Oct, 2024 - Comments: 0

A technical paper titled "Flexible electronic-photonic 3D integration from ultrathin polymer chiplets" was published by researchers at Dartmouth College and Boston University. The paper states: "Here, we present a robust chiplet-level heterogeneous integration of polymer-based circuits (CHIP), where ultrathin polymer electronic and optoelectronic chiplets are vertically bonded at room tempe... » read more

Working With Chiplets
By Ed Sperling - 02 Oct, 2024 - Comments: 0

The usual method of migrating to the next process node to cram more features onto a piece of silicon no longer works. It's too expensive, and too limited for most applications. The path forward is now heterogeneous chiplets targeted at specific markets, and while logic will continue to scale, other features are being separated out into chiplets developed using different process technologies. Th... » read more

Data Routing In Heterogeneous Chip Designs
By Ed Sperling - 30 Sep, 2024 - Comments: 0

Ensuring data gets to where it's supposed to go at exactly the right time is a growing challenge for design engineers and architects developing heterogeneous systems. There is more data moving around these chips with dozens of targets, which makes routing signals much more complicated. Ronen Perets, senior product marketing manager at Cadence Design Systems, talks about some of the new problems... » read more

Barriers To Chiplet Sockets
By Brian Bailey - 30 Sep, 2024 - Comments: 0

Experts At The Table: Demand for chiplets is growing, but debate continues about whether standards and general-purpose chiplets will kick-start the commercialization boom, or whether success will come through customization of those chiplets. Semiconductor Engineeering sat down to discuss these and other related issues with Elad Alon, CEO of Blue Cheetah; Mark Kuemerle, vice president of technol... » read more

Enabling Innovative Multi-Vendor Chiplet-Based Designs
By Elad Alon - 26 Sep, 2024 - Comments: 0

Chiplets have emerged as a critical implementation paradigm for semiconductor products, primarily because they can deliver cost benefits relative to a non-chiplet-based approach. The first, most well-proven, and obvious benefit of a chiplet-based approach is manufacturing cost. Manufacturing cost benefits are accrued either from the appropriate selection of chiplet die size, or by optimizin... » read more

Using AI To Glue Disparate IC Ecosystem Data
By Ed Sperling and Ann Mutschler - 26 Sep, 2024 - Comments: 0

AI holds the potential to change how companies interact throughout the global semiconductor ecosystem, gluing together different data types and processes that can be shared between companies that in the past had little or no direct connections. Chipmakers always have used abstraction layers to see the bigger picture of how the various components of a chip go together, allowing them to pinpoi... » read more

Optimizing Wafer Edge Processes For Chip Stacking
By Laura Peters - 23 Sep, 2024 - Comments: 0

Stacking chiplets vertically using short and direct wafer-to-wafer bonds can reduce signal delay to negligible levels, enabling smaller, thinner packages with faster memory/processor speeds and lower power consumption. The race is on to implement wafer stacking and die-to-wafer hybrid bonding, now considered essential for stacking logic and memory, 3D NAND, and possibly multi-layer DRAM stac... » read more

How Die Dimensions Challenge Assembly Processes
By Anne Meixner - 19 Sep, 2024 - Comments: 1

Multi-die assemblies are becoming more common and more complex due to technology advancements and market demands, but differing die dimensions are making this process increasingly challenging. To fully enable a multi-chiplet ecosystem, standardized component handling and interfaces are needed. The underlying concept is similar to LEGO blocks that simply snap together, yet it's nowhere near t... » read more

What Comes After HBM For Chiplets
By Brian Bailey - 18 Sep, 2024 - Comments: 0

Experts At The Table: Semiconductor Engineering sat down to discuss what will trigger the creation of a commercial chiplet marketplace, and what those chiplet-based designs will look like, with Elad Alon, CEO of Blue Cheetah; Mark Kuemerle, vice president of technology at Marvell; Kevin Yee, senior director of IP and ecosystem marketing at Samsung; Sailesh Kumar, CEO of Baya Systems; and Tanuja... » read more

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