EDA On Cloud Presents Unique Challenges

By Ann Mutschler - 31 Mar, 2022 - Comments: 0

Discussions about cloud-based EDA tools are heating up for both hardware and software engineering projects, opening the door to vast compute resources that can be scaled up and down as needed. Still, not everyone is on board with this shift, and even companies that use the cloud don't necessarily want to use it for every aspect of chip design. But the number of cloud-based EDA tools is growi... » read more

How To Justify A Data Center

By Ann Mutschler - 24 Mar, 2022 - Comments: 0

The breadth of cloud capabilities and improvements in cost and licensing structures is prompting chipmakers to consider offloading at least some of their design work into the cloud. Cloud is a viable business today for semiconductor design. Over the past decade, the interest in moving to cloud computing has grown from an idea that was fun to talk about — but which no one was serious about ... » read more

Assuring Reliable Processor Performance At Scale

By Uzi Baruch - 08 Mar, 2022 - Comments: 0

In today’s data center environment, resilience is key. Cloud providers are built on as-a-service business models, where uptime is critical to ensure their customers’ business continuity. Reputation and competitiveness require service at extremely high performance, low power, and increasing functionality, with zero tolerance for unplanned downtime or errors. If you’re a hyperscaler, o... » read more

Open RAN Direct RF Sampling Radio Transceiver Architectures For Massive MIMO

By AMD - 02 Mar, 2022 - Comments: 0

With the exponential increase in wireless traffic, mobile networks are transformed into more software-driven, virtualized, flexible, intelligent, and energy efficient systems. These trends have stimulated significant change in the core network with the advent of software defined networks (SDN) and network functions virtualization (NFV), which have enabled building more agile and less expensive ... » read more

Building Multipurpose Systems With Dynamic Function Exchange Part Two: Bundling And Managing Resources

By Ed Rebello - 03 Feb, 2022 - Comments: 0

In our previous article, we mentioned that one of the most-common oversights that designers can make is to not fully use available system resources, and we introduced you to the concept of Dynamic Function Exchange (DFX), a design approach that dynamically reallocates unused system resources to other tasks. From a technical standpoint, implementing DFX is relatively straightforward using a c... » read more

EDA In The Cloud Is Driving Semiconductor Innovation

By Nebabie Kebebew - 22 Dec, 2021 - Comments: 0

In the past decade, the move towards cloud computing occurred primarily in sectors like finance, retail, and healthcare, with the emergence of leading public cloud vendors such as Amazon Web Services (AWS), Microsoft Azure, Google Cloud Platform, and others accelerating the trend. However, the chip design industry has been slower to adopt cloud computing. In the current highly competitive en... » read more

Next Steps For Panel-Level Packaging

By Mark LaPedus - 20 Dec, 2021 - Comments: 1

Tanja Braun, group manager at Fraunhofer Institute for Reliability and Microintegration (IZM), sat down with Semiconductor Engineering to talk about III-V device packaging, chiplets, fan-out and panel-level processing. Fraunhofer IZM recently announced a new phase of its panel-level packaging consortium. What follows are excerpts of that discussion. SE: IC packaging isn’t new, but years a... » read more

Enablers And Barriers For Connecting Diverse Data

By Anne Meixner - 09 Nov, 2021 - Comments: 0

More data is being collected at every step of the manufacturing process, raising the possibility of combining data in new ways to solve engineering problems. But this is far from simple, and combining results is not always possible. The semiconductor industry’s thirst for data has created oceans of it from the manufacturing process. In addition, semiconductor designs large and small now ha... » read more

Easier And Faster Ways To Train AI

By Bryon Moyer - 04 Nov, 2021 - Comments: 0

Training an AI model takes an extraordinary amount of effort and data. Leveraging existing training can save time and money, accelerating the release of new products that use the model. But there are a few ways this can be done, most notably through transfer and incremental learning, and each of them has its applications and tradeoffs. Transfer learning and incremental learning both take pre... » read more

Using ML In EDA

By Ed Sperling - 20 Sep, 2021 - Comments: 0

Machine learning is becoming essential for designing chips due to the growing volume of data stemming from increasing density and complexity. Nick Ni, director of product marketing for AI at Xilinx, examines why machine learning is gaining traction at advanced nodes, where it’s being used today and how it will be used in the future, how quality of results compare with and without ML, and what... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.

by Ed Sperling

Defining The Chiplet Socket

The industry may have started with the wrong approach for enabling a third-party chiplet ecosystem, but who will step in and fix it?

by Brian Bailey

EDA On Cloud Presents Unique Challenges

How To Justify A Data Center

Assuring Reliable Processor Performance At Scale

Open RAN Direct RF Sampling Radio Transceiver Architectures For Massive MIMO

Building Multipurpose Systems With Dynamic Function Exchange Part Two: Bundling And Managing Resources

EDA In The Cloud Is Driving Semiconductor Innovation

Next Steps For Panel-Level Packaging

Enablers And Barriers For Connecting Diverse Data

Easier And Faster Ways To Train AI

Using ML In EDA

NAND Flash Targets 1,000 Layers

Auto Chip Aging Accelerates In Hot Climates

FOPLP Gains Traction in Advanced Semiconductor Packaging

HBM Options Increase As AI Demand Soars

Is In-Memory Compute Still Alive?