Leti’s Next Focus

By Mark LaPedus - 19 Jul, 2018 - Comments: 0

Emmanuel Sabonnadière, chief executive of Leti, sat down with Semiconductor Engineering to discuss R&D trends, a new deal with Soitec, and the latest developments at the France-based research organization. Leti is a research institute of CEA Tech. What follows are excerpts of that conversation. SE: Leti recently formed an alliance with Soitec. Under the terms, Leti and Soitec are formin... » read more

Tuesday At DAC 2018

By Brian Bailey - 27 Jun, 2018 - Comments: 0

The morning starts with the Accellera Breakfast. Accellera has made some significant progress this year and we can expect to hear about the approval of the Portable Stimulus 1.0 specification later in the conference as well as the initial release of SystemC CCI as well as a proposal for the creation of an IP Security Assurance Working Group, which will discuss standards development to address s... » read more

Silicon CMOS Architecture For A Spin-based Quantum Computer

By Technical Paper Link - 24 Jan, 2018 - Comments: 1

Source: UNSW Sydney Authors: M. Veldhorst (1,2), H.G.J. Eenink (2,3) , C.H. Yang (2), and A.S. Dzurak (2) 1 Qutech, TU Delft, The Netherlands 2 Centre for Quantum Computation and Communication Technology, School of Electrical Engineering and Telecommunications,UNSW, Sydney, Australia 3 NanoElectronics Group, MESA+ Institute for Nanotechnology,University of Twente, The Netherlands Te... » read more

Inside FD-SOI And Scaling

By Mark LaPedus - 15 Jun, 2017 - Comments: 5

Gary Patton, chief technology officer at [getentity id="22819" comment="GlobalFoundries"], sat down with Semiconductor Engineering to discuss FD-SOI, IC scaling, process technology and other topics. What follows are excerpts of that conversation. SE: In logic, GlobalFoundries is shipping 14nm finFETs with 7nm in the works. The company is also readying 22nm FD-SOI technology with 12nm FD-SOI ... » read more

Design For Noise (DfN)

By Technical Paper Link - 04 Apr, 2017 - Comments: 0

By Riko Radojcic and Yanfeng Li Abstract: This white paper describes the typical characteristics of electrical noise, and summarizes the current standard practices for managing noise in semiconductor devices. The impact of the technology trends – and specifically CMOS scaling - on noise amplitude and circuit sensitivity to noise are presented, and the requirements for coping with this emergi... » read more

MEMS: Improving Cost And Yield

By Ed Sperling - 13 Mar, 2017 - Comments: 2

MEMS devices inspire awe on the design side. On the test and manufacturing side, they evoke a different kind of reaction. These are, after all, the intersection of mechanical and electrical engineering—a joining of two miniature worlds that are the basis of some of the most complex technology on the planet. But getting these devices to yield sufficiently, understanding what does or does no... » read more

Power State Switching Gets Tougher

By Ann Mutschler - 12 Jan, 2017 - Comments: 0

Power state switching delay is a key factor in minimizing power, and getting it right frequently means the difference between a successful design and a dead chip. But tradeoffs are intricate, complex and often involve judgment calls, making this a place where designs can go completely awry. For years, traditional, full-swing [gettech id="31093" comment="CMOS"] process technologies were used ... » read more

Executive Insight: Charlie Cheng

By Ed Sperling - 03 Nov, 2016 - Comments: 0

[getperson id="11073" comment="Charlie Cheng"], CEO of [getentity id="22135" e_name="Kilopass Technology"], sat down with Semiconductor Engineering to talk about the limitations of DRAM, how to get around them, and who's likely to do that. What follows are excerpts of that discussion. SE: What are the top market segments from a [getkc id="22" kc_name="memory"] standpoint? Cheng: The top o... » read more

All You Need Is Cache (Coherency) To Scale Next-Gen SoC Performance

By Kurt Shuler - 25 Aug, 2016 - Comments: 0

Life on the SoC performance front remains a withering battle sometimes, because things can seem fairly bleak. As transistor scaling becomes more expensive below 10-nanometer feature sizes, every day it becomes harder to double performance every 18-months or so and stay competitive. Nowhere is the pain of this battle more acute than in consumer and automotive systems, where low cost is the key t... » read more

Ray Zinn Reflects On 37 Years As CEO Of Micrel

By Brian Bailey - 26 May, 2016 - Comments: 0

Believed to be the longest serving CEO of any company to have existed in Silicon Valley, Ray Zinn does more in retirement than many people would accomplish as full time employees. While his name may not be at the top of most influential people in the valley, the industry may not be the same today had it not been for his contributions. Semiconductor Engineering spoke with him about his past, the... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

tag: CMOS