tag: CMP

Inspection, Metrology Challenges Grow For SiC
By Mark LaPedus - 11 Jun, 2019 - Comments: 2

Inspection and metrology are becoming more critical in the silicon carbide (SiC) industry amid a pressing need to find problematic defects in current and future SiC devices. Finding defects always has been a challenging task for SiC devices. But it’s becoming more imperative to find killer defects and reduce them as SiC device vendors begin to expand their production for the next wave of a... » read more

Variation’s Long, Twisty Tail Worsens At 7/5nm
By Ed Sperling - 20 Sep, 2018 - Comments: 1

Variation is becoming a bigger challenge at each new node, but not just for obvious reasons and not always from the usual sources. Nevertheless, dealing with these issues takes additional time and resources, and it can affect the performance and reliability of those chips throughout their lifetimes. At a high level, variation historically was viewed as a mismatch between what design teams in... » read more

Manufacturing Bits: Aug. 7
By Mark LaPedus - 07 Aug, 2018 - Comments: 0

DNA ROMs The National Science Foundation (NSF) and the Semiconductor Research Corp. (SRC) are investing $12 million to develop a new class of memories and other technologies, such as DNA-based read-only memory (ROM), nucleic acid memory (NAM) and neural networks based on yeast cells. The effort is called the Semiconductor Synthetic Biology for Information Processing and Storage Technologies... » read more

More Lithography/Mask Challenges (Part 2)
By Mark LaPedus - 17 Apr, 2018 - Comments: 3

Semiconductor Engineering sat down to discuss lithography and photomask technologies with Gregory McIntyre, director of the Advanced Patterning Department at [getentity id="22217" e_name="Imec"]; Harry Levinson, senior fellow and senior director of technology research at [getentity id="22819" comment="GlobalFoundries"]; Regina Freed, managing director of patterning technology at [getentity id="... » read more

EUV’s New Problem Areas
By Mark LaPedus - 19 Mar, 2018 - Comments: 2

Extreme ultraviolet (EUV) lithography is moving closer to production, but problematic variations—also known as stochastic effects—are resurfacing and creating more challenges for the long-overdue technology. GlobalFoundries, Intel, Samsung and TSMC hope to insert [gettech id="31045" comment="EUV"] lithography into production at 7nm and/or 5nm. But as before, EUV consists of several compo... » read more

Silicon Photonics: Solving Process Variation And Manufacturing Challenges
By Sandy Wen - 17 Aug, 2017 - Comments: 0

As silicon photonics manufacturing gains momentum with additional foundry and 300mm offerings, process variation issues are coming to light. Variability in silicon processing affects the waveguide shape and can result in deviation in effective indices, propagation loss, and coupling efficiency from the intended design. In this article, we will highlight process variation issues that can occur i... » read more

ECO Fill Can Rescue Your SoC Tapeout Schedule
By Vikas Gupta - 16 Feb, 2017 - Comments: 0

By Vikas Gupta and Bhavani Prasad Integrated circuit (IC) design and manufacturing is one of the most challenging engineering industries. As soon as a design engineer gets into “the groove” and feels comfortable taping out in a particular technology node, the next technology node shrink is already there to pose a new and greater set of challenges. While it almost goes without saying that... » read more

Politics And (Low) Power
By Ed Sperling - 10 Nov, 2016 - Comments: 4

This week the entire semiconductor market woke up with a severe political hangover. Aside from the initial shock of the election results themselves, the winning platform of "America First" could have far-reaching implications for an industry that has spent decades optimizing a global supply chain the way it has finely tuned other processes to reduce the cost per transistor. There are many un... » read more

Creating An Accurate FEOL CMP Model
By Jeff Wilson - 20 Oct, 2016 - Comments: 0

By Ruben Ghulghazaryan, Jeff Wilson, and Ahmed AbouZeid For decades, semiconductor manufacturers have used chemical-mechanical polishing (CMP) as the primary technique for the smoothing and leveling (planarization) of dielectrics and metal layers. CMP modeling allows  design and manufacturing teams to find and fix potential planarization issues before the actual CMP process is applied to a ... » read more

A Novel Approach To Dummy Fill For Analog Designs Using Calibre SmartFill
By Mentor, a Siemens Business - 19 Oct, 2016 - Comments: 0

With small geometry silicon processes, additional nonfunctional geometric structures are required to maintain layer planarity during the chemical/mechanical polishing (CMP) phase of processing. The automated layout flows to generate such geometries tend to be designed primarily for large system on chip (SOC) digital designs. When applied to mixed-signal layouts, these flows have been seen to ha... » read more

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