Inspection, Metrology Challenges Grow For SiC

Defects, scale remain problematic, but new tools may help.


Inspection and metrology are becoming more critical in the silicon carbide (SiC) industry amid a pressing need to find problematic defects in current and future SiC devices.

Finding defects always has been a challenging task for SiC devices. But it’s becoming more imperative to find killer defects and reduce them as SiC device vendors begin to expand their production for the next wave of applications, particularly battery-electric vehicles.

So SiC device makers will need to bolster their process control measures with more inspection and metrology in the fab. Fortunately, the inspection and metrology equipment for SiC has recently become available, but these tools add cost to the fab equation. Generally, inspection systems locate defects on the wafer, while metrology tools characterize the structures in devices. Both technologies are used to pinpoint problems and ensure yields for all chip types.

SiC, a compound semiconductor material based on silicon and carbon, is used to make specialized power semiconductors for high-voltage applications, such as electric vehicles, power supplies and solar inverters. SiC has several advantages over conventional silicon-based power semis like IGBTs and power MOSFETs. But the silicon-based solutions dominate the market because they are less expensive than SiC.

In recent times, SiC device makers completed a difficult transition from 100mm (4-inch) to 150mm (6-inch) wafers in the fab. Some vendors, though, are still struggling with their yields and defect levels at 150mm. A few vendors have overcome most of these challenges, however.

Amid the challenges in the market, SiC device makers are now seeing an increase in demand for battery-electric cars. For years, SiC vendors have served the automotive market to a limited degree. But for next-generation electric vehicles, the industry will need to bring the technology to the next level and meet the industry’s rigid reliability, defect and cost specs.

“Yield improvement is critical for the significant market adoption of SiC, as this ultimately reflects into device pricing and positioning to bring SiC closer to IGBT market pricing,” said Llewellyn Vaughan-Edmunds, director of strategic marketing at Applied Materials.

There is another way to look at the situation. “As evidenced by Cree’s recent announcement to invest $1 billion to build out capacity for SiC, it’s becoming clear that SiC and GaN are no longer cottage industries,” said Jed Dorsheimer, an analyst at Canaccord Genuity. “The tight specifications of the auto industry would require greater metrology and compliance of SiC- and GaN-based devices for mission-critical applications.”

In May, Cree announced a major expansion plan for both SiC and the RF gallium-nitride (GaN). RF GaN is targeted for 5G wireless networks and other apps, while SiC is heating up for automotive. This article will focus on SiC, where a number of vendors are expanding and face several challenges.

SiC challenges
Suppliers of SiC devices include Infineon, Littlefuse, Microchip, On Semiconductor, STMicroelectronics, Rohm and Cree’s Wolfspeed unit.

SiC power semis are one of many types of power devices in the market. Some power semis are specialized transistors, which operate as a switch in systems. They allow the power to flow in the “on” state and stop it in the “off” state. These devices boost the efficiencies and minimize the energy losses in systems.

Power semiconductors based on SiC are considered wide bandgap technologies, which means they provide faster switching speeds and higher breakdown voltages than silicon-based solutions.

Typically, device makers sell SiC power MOSFETs and SiC diodes, which are used in 600-volt to 10-kilovolt applications. A SiC power MOSFET is a power switching transistor. A diode is a device that passes electricity in one direction and blocks it in the opposite direction.

SiC is taking off in battery-electric cars and other apps. The devices, which are used in various places in the car, are designed to boost efficiencies of the vehicle.

“The adoption of SiC technologies by leading manufacturers of electric vehicles and electric hybrid vehicles has significantly increased,” said David Haynes, senior director of strategic marketing at Lam Research. “Another emerging application is in the creation of the smart power grid infrastructure. This is particularly true in China where smart grid applications, along with automotive and high-speed rail applications, are expected to create a significant demand for SiC devices.”

SiC isn’t new. In fact, it’s been in the works for years. Starting in 2005, the industry began to produce SiC power devices in 100mm fabs. Then, from 2016 to 2017, device makers completed the migration from 100mm to 150mm fabs. Today, 150mm is the mainstream wafer size in SiC, with 200mm (8-inch) fabs in the works.

The transition from 100mm to 150mm was difficult. “Looking back to when most SiC semiconductor manufacturers migrated from 4-inch to 6-inch SiC wafers, the speed of the shift caught the SiC wafer suppliers by surprise,” said Richard Eden, an analyst with IHS Markit. “It is not an easy task to scale up the diameter of a wafer while maintaining high quality and yields. One or two suppliers are still struggling to achieve that even today.”

Others are ahead of the 150mm curve. “Our manufacturing team has just knocked it out of the park in terms of expanding the capacity and doing it at not only an incredible pace, but with super high-quality,” said Gregg Lowe, chief executive of Cree, in a recent conference call. “In fact, yields that we’re getting out of our factories right now in silicon carbide production and the wafer fabs and so forth are at record highs.”

Cree and its Wolfspeed unit have a long history with SiC, and they have been shipping products for years. Others are struggling in what is considered a challenging manufacturing process.

In the production flow, high-purity SiC materials are lowered into a crucible and heated. This, in turn, creates an ingot, which is then pulled and sliced into SiC substrates. Then, a thin epitaxial layer is grown on the substrate using a deposition process. The resulting substrate is then processed in the fab to make a power device.

The first big challenge is making the substrate. “The main challenge for SiC manufacturing relates to its material properties,” Applied’s Vaughan-Edmunds said. “SiC is almost as hard as diamond material and requires higher temperatures, higher energies and more time for crystal growth and processing. SiC is grown very slowly to form a 4-/6-inch boule about 35-50mm high. Typically, 15-20mm of that is single crystalline, where 15-20 wafers can be used for each boule. Compare this to a silicon ingot, utilizing the Czochralski process, (the ingot) can be up to 2 meters high and produce around 2,000 wafers each.”

There are other challenges. “4H-SiC is the most common polytype used today for a variety of power device applications,” said Mukund Raghunathan, product marketing manager at KLA. “It’s transparency and high refractive index makes it a challenging material to inspect for surface defects that may potentially impact epitaxy growth or final device yield.”

During the manufacturing flow, SiC substrates are prone to various defect types, such as crystalline stacking faults, micropipes, pits, scratches, stains and surface particles. A micropipe is a type of helical dislocation.

In addition, a network of tiny particle-like defects can surface on substrates. Moreover, the substrates are also prone to scratches. “Scratches are critical defects of interest on SiC substrates as they may lead to crystal defects like triangles, stacking faults, basal plane dislocations and step bunching post epitaxy. Due to this, proper polishing of silicon carbide substrate wafers is critical,” Raghunathan said. “Stacking faults on substrates transfer to epitaxy and may impact performance of certain devices. In general, we have seen a higher density of stacking faults on 150mm wafers than 100mm.”

Meanwhile, once the substrates are made, they are processed into devices in the fab. The processed wafers are diced and packaged. “There are challenges associated with SiC as it has proved difficult to handle, grind and saw, compared to silicon,” said Rich Rice, senior vice president of business development at ASE.

The dicing process is difficult. “Silicon carbide is the third hardest compound material on earth with a material hardness of 9.5 on the Mohs scale,” said Meng Lee, director of product marketing at Veeco. “Due to the high hardness and brittleness of SiC, manufacturers are facing cycle time, cost and dicing performance challenges.”

Now, Cree, Rohm and others are developing the next wafer size for SiC—200mm. 200mm SiC fabs won’t move into production until 2022, according to IHS.

200mm will present some challenges for SiC vendors. “Each increment in wafer size brings with it significant issues,” said Peter Gammon, an associate professor at the University of Warwick. “The first issue is material quality—getting the growth and epitaxy quality back up to the level of the previous generation, which is a case of reducing defect densities again. (Today, 6-inch defect densities far exceed those of 4-inch). The second issue is upgrading or retooling fabs that may have been designed for the state-of-the-art of the day or implementing new processes,”

That’s not the only challenge for 200mm. “Both fab retooling and improvement in the infrastructure is required at an exponential cost,” added Vishal Ajit Shah, an associate professor at the University of Warwick. “For example, SiC epitaxial CVD is performed at high temperatures not used for silicon (more than 1,500º C). So scaling this hot zone may need a new infrastructure with electricity costs not associated with silicon.”

Inspection/metrology challenges
Silicon carbide started out in a much more limited application. “It was more for military hardware,” said Subodh Kulkarni, president and CEO of CyberOptics. “Now, it’s becoming much more consumer, particularly with the introduction of electric vehicles.”

Generally, in automotive, there are stringent reliability and cost requirements for device makers. “The reliability of devices for automotive applications should be guaranteed by having suitable approvals, such as AEC-Q101,” said IHS’ Eden.

So vendors must adhere to strict process controls in the fab. It also requires an extensive device screening process using an assortment of inspection and metrology tools in the fab.

The tool types depend on the devices. In logic chips, for example, chipmakers use e-beam and optical systems to find defects on wafers. In addition, the logic industry uses a dozen or more metrology tool types.

SiC has different requirements than logic, but defect detection is also important. “In order to meet the forecast demand of wafers for power devices, the SiC wafer supply chain needs to develop a means to drive the cost of production down,” said David Jacques, product manager at Bruker. “This will be met through unified and more controlled wafer specifications using improved or new metrology tools that characterize the quality of the materials and allow better understanding of device failures. It is critical to develop new metrology techniques that are capable of detecting these defects in order to understand how they form in the crystal, with an end goal of reducing or eliminating them.”

In logic, the inspection and metrology steps are conducted throughout the process flow. The same is true for SiC. “Generally, wafer defect inspection is necessary for the status of the seed crystal process,” said Hirokazu Seki, a director at Lasertec. “It is also required after CMP, after epitaxial growth and after annealing. This is because killer defects can not only surface on the substrate, but they are generated or transformed by high-temperature and CMP processes. It is also known that some processes can damage the wafer, which generates killer defects.”

For SiC, there is no one tool that can handle all inspection/metrology tasks—it requires several systems to do the job. For example, optical techniques are used for defect inspection. Photoluminescence and X-ray are used for metrology. Other tools are used as well.

All tool types face similar challenges. “In terms of inspection of the wafer or epi layer, the main thing is throughput versus detail,” Warwick’s Shah said. “The other important parameter is being able to discern defects throughout the wafer thickness and also at the surface.”

The current defect detection tools for SiC claim to have high throughputs with other advantages, but there is cost associated with them. “Some of these can produce figures for surface roughness and large scale defects, but these densities are low in production-grade 100mm and 150mm wafers,” Shah said. “If funds are not limited, you can afford one of these tools. There is a small race to make these tools faster and cheaper.”

Meanwhile, on one front, KLA and Lasertec sell systems that combine two technologies—surface defect inspection and photoluminescence metrology. Photoluminescence is a non-contact spectroscopy technique, which looks at the crystal structures of devices.

Surface defect inspection uses optical imaging. For example, in its tool, Lasertec incorporates confocal and differential interference contrast optics for surface optical imaging. “The main challenge for SiC wafer optical defect inspection is to enable effective process monitoring and control as well as yield prediction by detection and classification of critical defect types that are not always visible on the surface of the wafer at a very high throughput,” Lasertec’s Seki said. “Confocal system optics avoid false detections from the wafer backside even for a transparent wafer such as SiC. Differential interference contrast realizes clear visualization of shallow defects at nanometer depths.”

Photoluminescence metrology capabilities are also critical in these systems. “Ideally, defect inspection systems for SiC should have the capability to detect critical surface and sub-surface defects on SiC substrate and epitaxial layers,” KLA’s Raghunathan said. “What adds to the complexity is that many of the defect types are sub-surface and can be measured only using photoluminescence.”

In the photoluminescence mode, the wavelength in the system is selected such that it penetrates through the epi layer to give a signal. “The bandgap of 4H-SiC is ~3.2eV (~385nm),” Raghunathan said. “So wavelengths around 355nm are ideal for SiC inspection since photoluminescence becomes active when excited with wavelengths below the bandgap, and the penetration depth is only ~50µm at 355nm.”

Fig. 1: Integrated surface and photoluminescence channels for SiC epitaxy defect detection. Source: KLA

Both surface inspection and photoluminescence capabilities are used for various reasons. “On epitaxial wafers, there are many types of crystal defects with different kill ratios,” Raghunathan said. “What makes SiC even more interesting is that the kill ratio for each defect type changes depending on the end application. For example, a basal plane defect is a reliability killer for power MOSFETs, but it has no impact on Schottky diodes.”

The general idea is to look at the reflected light and infer information about the die surface. “With silicon, silicon nitride and silicon carbide, reflections make a big difference,” said CyberOptics’ Kulkarni. “We are using reflecting distortion to detect subtle surface structures and different silicon structures.”

More detection
Meanwhile, X-ray metrology is also used for SiC, namely X-ray diffraction imaging (XRDI). “Crystalline defects induce changes to the spacing (strain) and/or the rotation (tilt) of the crystal lattice around them, forming a strain field,” Bruker’s Jacques said. “Based on Bragg’s X-ray diffraction, XRDI is a non-destructive technique that images the strain field induced by these defects by measuring the variation of the diffracted intensity across the wafer.”

XRDI is used for several reasons. “SiC crystal growth and device manufacturing have improved greatly, but the process yields are still hindered by the high densities of crystalline defects that are detrimental to device performance and their long-term reliability,” Jacques said. “The current techniques used to detect these crystalline defects in SiC wafers face several limitations. On one hand, etching processes using molten chemicals pose safety risks and are destructive, which stops the analyzed samples from being brought back into the process line. On the other hand, photoluminescence and scattering techniques have limited interaction with heavily n-doped substrates that are used for the most advanced SiC devices.”

XRDI also solves other issues. “It enables the non-destructive detection of the detrimental threading screw dislocations, threading edge dislocations, stacking faults and basal plane dislocations on all types of SiC wafers, including n+ doped substrates,” he said. “Moreover, XRDI also operates at a fast throughput, with a sufficient resolution and includes robotic wafer handling.”

Clearly, there are several fab challenges for SiC. The good news is that the equipment industry has responded with some innovative defect detection tools.

In addition, SiC device makers are also investing in new fabs and equipment. To meet demand, the industry requires a larger scale. It no longer can operate with a cottage mindset.


Allen Rasafar says:

Thank you for this in depth information about Metrology challenges for SiC wafer manufacturing.
I was hoping to learn about Bulk/Boule level crystalline measurement and analysis systems.

Allen Rasafar says:

I also would like to add AMD, II-VI as one the main suppliers of the SiC Poly type wafers.

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