Week In Review: Design, Low Power


Tools Mentor unveiled Tessent Streaming Scan Network software for its Tessent TestKompress software. The new solution includes embedded infrastructure and automation that decouples core-level DFT requirements from the chip-level test delivery resources for a simplified bottom-up DFT flow. The bus-based scan data distribution architecture enables simultaneous testing of any number of cores and ... » read more

Speeding Up AI With Vector Instructions


A search is underway across the industry to find the best way to speed up machine learning applications, and optimizing hardware for vector instructions is gaining traction as a key element in that effort. Vector instructions are a class of instructions that enable parallel processing of data sets. An entire array of integers or floating point numbers is processed in a single operation, elim... » read more

Using Verification Data More Effectively


Verification is producing so much data from complex designs that engineering teams need to decide what to keep, how long to keep it, and what they can learn from that data for future projects. Files range from hundreds of megabytes to hundreds of gigabytes, depending on the type of verification task, but the real value may not be obvious unless AI/machine learning algorithms are applied to a... » read more

Embedded Processor Requirements And OS Choice


For each embedded product, software developers need to consider whether they need an operating system; and if so, what type of an OS. Operating systems vary considerably, from real-time operating systems with a very small memory footprint to general-purpose OSes such as Linux with a rich set of features. Choosing a proper type of operating system for your product – and consequently w... » read more

Week In Review: Design, Low Power


Arm spun out Cerfe Labs to develop and license new types of non-volatile memories based on correlated electron materials (CeRAM) and ferroelectric transistors (FeFETs). Arm CeRAM researchers will join Cerfe Labs and assume ownership of the Arm joint development project with Symetrix Corporation. Read more about the new company and its technology in Cerfe Labs: Spin-On Memory. Tools & IP ... » read more

RISC-V: Will There Be Other Open-Source Cores?


Part 3: Semiconductor Engineering sat down to discuss the business and technology landscape for RISC-V with Zdenek Prikryl, CTO of Codasip; Helena Handschuh, a Rambus Security Technologies fellow; Louie De Luna, director of marketing at Aldec; Shubhodeep Roy Choudhury, CEO of Valtrix Systems; and Bipul Talukdar, North America director of applications engineering at SmartDV. What follows are exc... » read more

New Uses For Assertions


Assertions have been a staple in formal verification for years. Now they are being examined to see what else they can be used for, and the list is growing. Traditionally, design and verification engineers have used assertions in specific ways. First, there are assertions for formal verification, which are used by designers to show when something is wrong. Those assertions help to pinpoint wh... » read more

Defining Processor Core Complexity


The more complex a processor core, the larger the area and power consumption. But increasing complexity is not a single dimension, as processors can be more complex in different ways. In selecting a processor IP core, it is important to choose the right sort of complexity for your project. Some ways of thinking about complexity include: Word length Execution units Privilege/prot... » read more

Creating Domain-Specific Processors Using Custom RISC-V ISA Instructions


When System-on-Chip (SoC) developers include processors in their designs, they face choices in solving their computational challenges. Complex SoCs will usually have a variety of processor cores responsible for varied functions such as running the main application programs, communications, signal processing, security, and managing storage. Traditionally, such cores have been in distinct categor... » read more

RISC-V: What’s Missing And Who’s Competing


Part 2: Semiconductor Engineering sat down to discuss the business and technology landscape for RISC-V with Zdenek Prikryl, CTO of Codasip; Helena Handschuh, a Rambus Security Technologies fellow; Louie De Luna, director of marketing at Aldec; Shubhodeep Roy Choudhury, CEO of Valtrix Systems; and Bipul Talukdar, North America director of applications engineering at SmartDV. What follows are exc... » read more

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