Week In Review: Design, Low Power

CeRAM spin out; Arm’s roadmap for client CPUs; new IP from Synopsys, Cadence and Codasip.


Arm spun out Cerfe Labs to develop and license new types of non-volatile memories based on correlated electron materials (CeRAM) and ferroelectric transistors (FeFETs). Arm CeRAM researchers will join Cerfe Labs and assume ownership of the Arm joint development project with Symetrix Corporation. Read more about the new company and its technology in Cerfe Labs: Spin-On Memory.

Tools & IP
Arm outlined its roadmap for Client CPUs: Matterhorn and Makalu will debut in 2021 and 2022, respectively, with Makalu having an expected performance uplift of up to 30% from the current Cortex-A78. Matterhorn will introduce the Memory Tagging Extension (MTE) feature to tighten security vulnerabilities that can occur in memory subsystems. Arm is also pushing mobile to move entirely to 64-bit, and said that starting with its 2022 IP, all future Cortex-A “big” cores will only support 64-bit.

Synopsys’ DesignWare CXL Controller IP now supports the AMBA CXS protocol for integration with the latest Arm Neoverse Coherent Mesh Network and multichip IP stacks. The CXL IP operates at at 32GT/s with 512-bit data width, supports all the required CXL protocol types (.cache, .io, and .mem) and allows mixing multiple types within a single clock-cycle transfer for design flexibility.

Cadence IP supporting the DDR5 and LPDDR5 DRAM memory standards is now available silicon-proven on TSMC’s N5 process. IP for GDDR6 is immediately available on both N6 and N7 and forthcoming for TSMC N5. The IP includes Cadence PHY and controller Design IP and Verification IP (VIP) and support a variety of applications including data center, AI/ML, hyperscale computing, storage, and automotive. In addition, Cadence’s Pegasus Verification System was certified for TSMC’s N16, N12 and N7 process technologies.

Codasip released the latest versions of its Studio processor IP generation tool and CodeSpace firmware development environment. Versions 8.4.0 add WFI automation, interconnect, and parametrized RTL capabilities.

Intento Design introduced IDX-PVT, an expansion of its ID-Xplore analog design tool. IDX-PVT automates design centering to deal with process variation while taking into account design corners and PPA requirements.

VSORA unveiled a combination multi-core DSP and ML acceleration platform for L4/L5 autonomous driving. The AD1028 IP provides computational power of 1,028 TeraFLOPS or one PetaFLOPS running at 2GHz, and the company says it can process eight-million pixel images on a Yolo-v3 in less than 7 ms and a full HD image in less than 1.6 ms.

Think Silicon extended its IP portfolio with a new inference Micro GPU Architecture based on the RISC-V ISA  with the Graphic Vector extension and customized user defined instructions for AI-Vision and graphics tasks. Configurable to up to 64 scalable shader cores, it targets bare metal/RTOS to Linux systems.

CAST uncorked a new IP core that implements a switch for Time-Sensitive Networking (TSN) Ethernet networks. The TSN-SW TSN Ethernet Switch core is architected for ultra-low latency, a small silicon area, supports Linux and FreeRTOS drivers, and is available as synthesizable RTL or targeted netlists. The core was developed by Fraunhofer IPMS.

Deals & Education
Edaptive Computing Inc. and OneSpin Solutions launched a Formal Verification Certification Program to provide comprehensive training of formal methods theory, techniques and their application to real-world hardware designs using the OneSpin Design Verification 360 Solutions. The program covers beginner, intermediate, and advanced training levels.

Cummins is using Ansys tools and simulation process and data management (SPDM) platform in its research related to improving emissions profiles, performance and other attributes of diesel and alternative fuel engines. Cummins noted that Ansys has been an R&D partner for over 25 years.

Numbers & People
EDA and IP revenue increased 12.6% in Q2 2020 to $2.78 billion, up from $2.47 billion in the same period in 2019, according to the ESD Alliance Market Statistics Service. By category, CAE increased 16.1% to $922 million compared to Q2 2019. IC physical design and verification was up 16.8% to $584 million, and semiconductor IP grew 13.6% to $948 million. PCB revenue was flat at 0.3%, while services revenue dipped 12.8%. The industry is still hiring: employment in tracked companies was up 5% from Q2 2019 and 1.4% from Q1 2020.

Simon Beresford-Wylie is joining Imagination Technologies as the company’s new Chief Executive Officer. Beresford-Wylie was previously Chief Executive of UK telecom company Arqiva. Prior to Arqiva he was Global Executive Advisor and Executive Vice President to the Networks Business Unit of Samsung Electronics. Beresford-Wylie has also been founding CEO of Nokia Siemens Networks, and sat on the boards of Nokia Corporation and the Vitec Group. He replaces interim CEO Ray Bingham, who will remain Imagination’s Executive Chairman.

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