Balancing Memory And Coherence: Navigating Modern Chip Architectures

By Frank Schirrmeister - 21 Dec, 2023 - Comments: 0

In the intricate world of modern chip architectures, the "memory wall" – the limitations posed by external DRAM accesses on performance and power consumption growing slower than the ability to compute data – has emerged as a pivotal challenge. Architects must strike a delicate balance between leveraging local data reuse and managing external memory accesses. While caches are critical for op... » read more

RISC-V Driving New Verification Concepts

By Brian Bailey - 12 Apr, 2023 - Comments: 0

Semiconductor Engineering sat down to discuss gaps in tools and why new methodologies are needed for RISC-V processors, with Pete Hardee, group director for product management at Cadence; Mike Eftimakis, vice president for strategy and ecosystem at Codasip; Simon Davidmann, founder and CEO of Imperas Software; Sven Beyer, program manager for processor verification at Siemens EDA; Kiran Vittal, ... » read more

Reducing The Cost of Cache Coherence By Integrating HW Coherence Protocol Directly With The Programming Language

By Technical Paper Link - 19 Mar, 2023 - Comments: 0

A new technical paper titled "WARDen: Specializing Cache Coherence for High-Level Parallel Languages" was published by researchers at Northwestern University and Carnegie Mellon University. Abstract: "High-level parallel languages (HLPLs) make it easier to write correct parallel programs. Disciplined memory usage in these languages enables new optimizations for hardware bottlenecks, such ... » read more

The New CXL Standard

By Ed Sperling - 16 Sep, 2019 - Comments: 0

Gary Ruggles, senior staff product marketing manager at Synopsys, digs into the new Compute Express Link standard, why it’s important for high bandwidth in AI/ML applications, where it came from, and how to apply it in current and future designs. » read more

Impacts Of Reliability On Power And Performance

By Ann Mutschler - 13 Dec, 2018 - Comments: 0

Making sure a complex system performs as planned, and providing proper access to memories, requires a series of delicate tradeoffs that often were ignored in the past. But with performance improvements increasingly tied to architectures and microarchitectures, rather than just scaling to the next node, approaches such as determinism and different kinds of caching increasingly are becoming criti... » read more

Coherency: The New Normal In SoCs

By NetSpeed Systems - 26 Oct, 2016 - Comments: 0

We are not far from devices each handling 100 teraflops of compute, billions of pixels of display, hundreds of gigabits of connectivity, and terabytes of storage. Compared with current state-of-the-art mobile SoCs, these are increases of one or two orders of magnitude — at similar or preferably lower power consumption. SoC design is changing to meet this challenge. Multicore architecture i... » read more

Adapt Or Perish: A Unified Theory Of Coherency

By Rajesh Ramanujam - 28 Jul, 2016 - Comments: 0

Evolution is a natural process and more importantly a relatively slow process that has eventually got us here, capable of perceiving, analyzing, and handling complex tasks. As our environment, society, and surroundings became more complex we learned how to adapt at a brisk and instantaneous manner, in this melting pot of a heterogeneous world. The evidence can be seen in all ages, from the poli... » read more

The Mightier Microcontroller

By Ed Sperling - 26 May, 2016 - Comments: 1

Microcontrollers are becoming more complex, more powerful, and significantly more useful, but those improvements come with strings attached. While it's relatively straightforward to develop multi-core microcontroller (MCU) hardware with advanced power management features, it's much more difficult to write software for these chips because memory is limited. CPUs can use on-chip memory such as... » read more

What Is Coherency?

By Neil Parris - 09 Apr, 2015 - Comments: 0

Coherency is about ensuring all processors, or bus masters in the system see the same view of memory. Cache coherency means that all components have the same view of shared data. Just as you need both of your eyes to have the same view in order to see properly, it’s critical for every IP block that has access to a shared data source to view consistent data. For example, if I have a process... » read more

Experts At The Table: Coherency

By Ed Sperling - 17 Aug, 2012 - Comments: 0

System-Level Design sat down to discuss coherency with Mirit Fromovich, principal solutions engineer at Cadence; Drew Wingard, CTO of Sonics; Mike Gianfagna, vice president of marketing at Atrenta, and Marcello Coppola, technical director at STMicroelectronics. What follow are excerpts of that conversation. SLD: We’ve been hearing a lot about Wide I/O. Why is it so important and what effec... » read more

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Knowledge Centers
Entities, people and technologies explored

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Partitioning In The Chiplet Era

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by Ann Mutschler

3.5D: The Great Compromise

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eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

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New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.