tag: Coventor

Understanding Advanced Packaging Technologies And Their Impact On The Next Generation Of Electronics
By Sandy Wen - 28 Aug, 2020 - Comments: 2

Chip packaging has expanded from its conventional definition of providing protection and I/O for a discrete chip to encompassing a growing number of schemes for interconnecting multiple types of chips. Advanced packaging has become integral to embedding increased functionality into a variety of electronics, such as cellular phones and self-driving vehicles, by supporting high device density in ... » read more

Process Model Calibration: Building Predictive and Accurate 3D Process Models
By Coventor - 20 Aug, 2020 - Comments: 0

The semiconductor industry has always faced challenges caused by device scaling, architecture evolution and process complexity and integration. These challenges are coupled with a need to provide new technology to the market quickly. In the initial stages of semiconductor technology development, innovative process flow schemes must be tested using silicon test wafers. These wafer tests are leng... » read more

Next Challenge: Parts Per Quadrillion
By Ed Sperling - 29 Jul, 2020 - Comments: 0

Requirements for purity of the materials used in semiconductor manufacturing are being pushed to unprecedented — and increasingly unprovable — levels as demand for reliability in chips over increasingly longer lifetimes continues to rise. And while this may seem like a remote problem for many parts of the supply chain, it can affect everything from availability of materials needed to make t... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 24 Jul, 2020 - Comments: 0

Semicon recap The virtual version of Semicon West took place this week. Virtual events have their places. It’s no substitute for an in-person event. Nonetheless, the virtual version of Semicon West is still a place to get an update on the latest equipment, test and packaging technologies. It is also interesting to visit the virtual booths. It’s a fast way to meet people. I chatted with ... » read more

Semicon West Day One/Two
By Mark LaPedus - 22 Jul, 2020 - Comments: 0

For years, the semiconductor and equipment industry has congregated at the annual Semicon West trade show in San Francisco. It’s an event to get an update on the latest equipment, test and packaging technologies. It’s also a good way to meet with people who you haven’t seen in a year, if not longer. It’s a great way to get a pulse on the industry. Needless to say, Semicon is a vir... » read more

Semiconductor Memory Evolution And Current Challenges
By Michael Hargrove - 16 Jul, 2020 - Comments: 0

The very first all-electronic memory was the Williams-Kilburn tube, developed in 1947 at Manchester University. It used a cathode ray tube to store bits as dots on the screen’s surface. The evolution of computer memory since that time has included numerous magnetic memory systems, such as magnetic drum memory, magnetic core memory, magnetic tape drive, and magnetic bubble memory. Since the 19... » read more

Speeding Up Process Optimization With Virtual Processing
By Coventor - 16 Jul, 2020 - Comments: 0

Advanced CMOS scaling and new memory technologies have introduced increasingly complex structures into the device manufacturing process. For example, the increase in NAND memory layers has achieved greater vertical NAND scaling and higher memory density, but has led to challenges in high aspect ratio etch patterning and foot print scaling issues. Unique integration and patterning schemes have b... » read more

Atomic Layer Etch Expands To New Markets
By Mark LaPedus - 16 Jul, 2020 - Comments: 0

The semiconductor industry is developing the next wave of applications for atomic layer etch (ALE), hoping to get a foothold in some new and emerging markets. ALE, a next-generation etch technology that removes materials at the atomic scale, is one of several tools used to process advanced devices in a fab. ALE moved into production for select applications around 2016, although the technolog... » read more

A Benchmark Study Of Complementary-Field Effect Transistor (CFET) Process Integration Options: Comparing Bulk vs. SOI vs. DSOI Starting Substrates
By Coventor - 17 Jun, 2020 - Comments: 0

Sub-5 nm logic nodes will require an extremely high level of innovation to overcome the inherent real-estate limitations at this increased device density. One approach to increasing device density is to look at the vertical device dimension (z-direction), and stack devices on top of each other instead of conventionally side-by-side. The fabrication of a Complementary-Field Effect Transistor (CF... » read more

Introducing Nanosheets Into Complementary-Field Effect Transistors (CFETs)
By Benjamin Vincent - 01 Jun, 2020 - Comments: 0

In our November 2019 blog [1], we discussed using virtual fabrication (SEMulator3D) to benchmark different process integration options for Complementary-FET (CFET) fabrication. CFET is a CMOS architecture that was proposed by imec in 2018 [2]. This architecture contains p- and n-MOSFET structures built on top of each other, instead of having them located side-by-side. In our previous blog, we r... » read more

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