tag: Coventor

Micro Loading And Its Impact On Device Performance
By Qingpeng Wang - 02 Nov, 2020 - Comments: 0

In a DRAM structure, the charging and discharging process of capacitor-based memory cells is directly controlled by the transistor [1]. With transistor sizes approaching the lower limits of physical achievability, manufacturing variability and micro loading effects are becoming increasingly critical DRAM performance (and yield) limiters. The transistor’s AA (active area) dimension and profile... » read more

Virtual Fabrication At 7/5/3nm
By Ed Sperling - 23 Oct, 2020 - Comments: 0

David Fried, vice president of computational products at Lam Research, digs into virtual fabrication at the most advanced nodes, how to create models using immature processes at new nodes, and how to fuse together data from multiple different silos. » read more

Defect Challenges Grow For IC Packaging
By Mark LaPedus - 22 Oct, 2020 - Comments: 0

Several vendors are ramping up new inspection equipment based on infrared, optical, and X-ray technologies in an effort to reduce defects in current and future IC packages. While all of these technologies are necessary, they also are complementary. No one tool can meet all defect inspection requirements. As a result, packaging vendors may need to buy more and different tools. For years, p... » read more

Winning The Global Race For Semiconductor Technology With Virtual Fabrication
By David Fried - 22 Oct, 2020 - Comments: 0

Semiconductor process development is no easy task, with each generation of devices more difficult and expensive to create. Traditional cycles of build-and-test development are becoming obsolete, since they are too expensive and time-consuming for the most advanced processes. The high cost of process development Most chip designers developing new products rely on existing manufacturing process... » read more

Much Smarter Manufacturing
By Ed Sperling - 22 Oct, 2020 - Comments: 0

Smart manufacturing is undergoing some fundamental changes as more sensors are integrated across fabs to generate more usable data, and as AI/ML systems are deployed to sift through that data and identify patterns and anomalies more quickly. The concept of smart manufacturing — also referred to as Industrie 4.0 in Europe, for the fourth industrial revolution — emerged from the World Econ... » read more

Impact Of EUV Resist Thickness On Local Critical Dimension Uniformities For <30nm CD Via Patterning
By Coventor - 21 Oct, 2020 - Comments: 0

This paper describes the impact of extreme ultraviolet (EUV) resist thickness on <30 nm via local critical dimension uniformity (LCDU) measured during after development inspection (ADI) and after etch inspection (AEI). For the same post-etch CD targets, increasing resist thickness from 40 to 60 nm helped reduced CD variability. This work was performed via virtual fabrication using Coventor�... » read more

Building Predictive And Accurate 3D Process Models
By Pradeep Nanja - 21 Sep, 2020 - Comments: 0

Process engineers and integrators can use virtual process modeling to test alternative process schemes and architectures without relying on wafer-based testing. One important aspect of building an accurate process model is to ensure that the model is calibrated. Having a calibrated model is important, since it provides assurance to the process integrators and engineers that the model will refle... » read more

Momentum Builds For Advanced Packaging
By Mark LaPedus - 17 Sep, 2020 - Comments: 0

The semiconductor industry is stepping up its efforts in advanced packaging, an approach that is becoming more widespread with new and complex chip designs. Foundries, OSATs and others are rolling out the next wave of advanced packaging technologies, such as 2.5D/3D, chiplets and fan-out, and they are developing more exotic packaging technologies that promise to improve performance, reduce p... » read more

Process Model Calibration: Building Predictive And Accurate 3D Process Models
By Coventor - 16 Sep, 2020 - Comments: 0

The semiconductor industry has always faced challenges caused by device scaling, architecture evolution and process complexity and integration. These challenges are coupled with a need to provide new technology to the market quickly. In the initial stages of semiconductor technology development, innovative process flow schemes must be tested using silicon test wafers. These wafer tests are leng... » read more

Understanding Advanced Packaging Technologies And Their Impact On The Next Generation Of Electronics
By Sandy Wen - 28 Aug, 2020 - Comments: 2

Chip packaging has expanded from its conventional definition of providing protection and I/O for a discrete chip to encompassing a growing number of schemes for interconnecting multiple types of chips. Advanced packaging has become integral to embedding increased functionality into a variety of electronics, such as cellular phones and self-driving vehicles, by supporting high device density in ... » read more

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