tag: Coventor

Blog Review: Oct. 24
By Jesse Allen - 24 Oct, 2018 - Comments: 0

Arm's Shidhartha Das digs into Power Delivery Networks with a look at how the specific roles of different components work to provide smooth supply conditions. In a video, VLSI Research's Dan Hutcheson chats with D2S CEO Aki Fujimura about the state of the photomask market, EUV optimism, and the most interesting findings from this year's eBeam Initiative survey. Synopsys' Prasad Subudhi K.... » read more

Lab-To-Fab Testing
By Ed Sperling - 08 Oct, 2018 - Comments: 0

Test equipment vendors are working on integrating testing and simulation in the lab with testing done later in the fab, setting the stage for what potentially could be the most significant change in semiconductor test in years. If they are successful, this could greatly simplify design for test, which has become increasingly difficult as chips get more complex, denser, and as more heterogene... » read more

Variation’s Long, Twisty Tail Worsens At 7/5nm
By Ed Sperling - 20 Sep, 2018 - Comments: 1

Variation is becoming a bigger challenge at each new node, but not just for obvious reasons and not always from the usual sources. Nevertheless, dealing with these issues takes additional time and resources, and it can affect the performance and reliability of those chips throughout their lifetimes. At a high level, variation historically was viewed as a mismatch between what design teams in... » read more

Using AI In Chip Manufacturing
By Ed Sperling - 22 Aug, 2018 - Comments: 0

David Fried, CTO at Coventor, a Lam Research Company, sat down with Semiconductor Engineering to talk about how AI and Big Data techniques will be used to improve yield and quality in chip manufacturing. What follows are excerpts of that conversation. SE: We used to think about manufacturing data in terms of outliers, but as tolerances become tighter at each new node that data may need to b... » read more

A Review of Silicon Photonics
By Michael Hargrove - 20 Aug, 2018 - Comments: 0

With the end of Moore’s Law rapidly approaching—some say it's already here—new applications of older technologies are gaining attention. One specific area of interest is photonics. The National Center for Optics and Photonic Education defines photonics as the technology of generating and harnessing light and other forms of radiant energy whose quantum unit is the photon. It can also be... » read more

Benefits And New Applications For FD-SOI
By Sofiane Guissi - 23 Jul, 2018 - Comments: 0

Over the past decades, transistor feature size has continuously decreased, leading to an increase in performance and a reduction in power consumption. Consumers have reaped the benefits, with superior electronic devices that have become increasingly useful, valuable, faster and more efficient. In recent years, as transistor feature size has shrunk below 10nm, it has become progressively more di... » read more

Practical Methods To Overcome The Challenges Of 3D Logic Design
By Benjamin Vincent - 25 Jun, 2018 - Comments: 0

What should you do If you don’t have enough room on your floor to store all your old boxes? Luckily, we live in a 3D world, and you can start stacking them on top of each other. The Challenge: How can we shrink logic devices? Logic designers are currently facing even bigger challenges than you might be having in tidying up your storage area. Not only are logic cells highly packed together... » read more

Dealing With Resistance In Chips
By Mark LaPedus - 21 Jun, 2018 - Comments: 2

Chipmakers continue to scale the transistor at advanced nodes, but they are struggling to maintain the same pace with the other two critical parts of the device—the contacts and interconnects. That’s beginning to change, however. In fact, at 10nm/7nm, chipmakers are introducing new topologies and materials such as cobalt, which promises to boost the performance and reduce unwanted resist... » read more

Big Trouble At 3nm
By Mark LaPedus - 21 Jun, 2018 - Comments: 0

As chipmakers begin to ramp up 10nm/7nm technologies in the market, vendors are also gearing up for the development of a next-generation transistor type at 3nm. Some have announced specific plans at 3nm, but the transition to this node is expected to be a long and bumpy one, filled with a slew of technical and cost challenges. For example, the design cost for a 3nm chip could exceed an eye-p... » read more

Transistor-Level Performance Evaluation Based On Wafer-Level Process Modeling
By Michael Hargrove - 30 May, 2018 - Comments: 0

Three years ago, I wrote a blog entitled “Linking Virtual Wafer Fabrication Modeling with Device-level TCAD Simulation,” in which I described the seamless connection between the SEMulator3D virtual wafer fabrication software platform and external third-party TCAD software. I’m now happy to report that device-level I-V performance analysis is now a built-in module within the SEMulator3D so... » read more

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