tag: critical dimension

3D NAND Needs 3D Metrology
By Nick Keller - 08 Aug, 2023 - Comments: 0

By Nick Keller and Andy Antonelli You’ve read the reports: the memory market is floundering as the semiconductor industry moves through another scarcity/surplus cycle. Be that as it may, innovation is happening as the industry continues to pursue increasingly higher three-dimensional stacks, with 3D NAND stacks taller than 200 layers entering production. However, there are challenges... » read more

A New Dimension In Optical CD
By Ilya Osherov - 15 Dec, 2022 - Comments: 0

One of the biggest challenges for nanoscale fabrication is how to measure devices on such a minute scale. As the semiconductor industry demands ever smaller devices, the need for reliable, robust measurements for quality control and process optimization increases. One robust and commonly used technique in semiconductor manufacturing is optical critical dimension (OCD) metrology. Standard, al... » read more

Critical Moves: Advanced Logic Devices And CIS Benefit From Applications Using IRCD Metrology
By Nick Keller - 08 Feb, 2022 - Comments: 1

As 3D NAND continues to scale vertically — all in the name of increasing capacity and speed and reducing inefficiency and cost — maintaining channel hole critical dimension (CD) and shape uniformity becomes even more challenging. Faced with rising high-aspect ratios, addressing these challenges requires new inline non-destructive metrology to provide real-time process control. Infrared crit... » read more

Better Inspection, Higher Yield
By Bryon Moyer - 08 Sep, 2020 - Comments: 0

Wafers can be inspected for large, obvious defects, or for small, subtle ones. The former is referred to as macro-inspection, while the latter is micro-inspection. These processes use different machines with different capital and operating costs, and they might look like competing approaches with different economic returns. In fact, they are complementary tactics that can be balanced within an ... » read more

Clean Focus, Dose And CD Metrology For CD Uniformity Improvement
By KLA - 11 Jun, 2019 - Comments: 0

Authors: Honggoo Leea, Sangjun Hana, Minhyung Honga, Seungyong Kima, Jieun Leea, DongYoung Leea, Eungryong Oha, Ahlin Choia, Nakyoon Kimb, John C. Robinsonc, Markus Mengelc, Pablo Rovirac, Sungchul Yooc, Raphael Getinc, Dongsub Choib, Sanghuck Jeonb aSK Hynix, 2091, Gyeongchung-daero, Bubal-eub, Icheon-si, Gyeonggi-do, 467-701, Korea bKLA-Tencor Korea, Starplaza bldg., 53 Metapolis-ro, Hwasung... » read more

Variation Issues Grow Wider And Deeper
By Ed Sperling - 24 Jan, 2019 - Comments: 0

Variation is becoming more problematic as chips become increasingly heterogeneous and as they are used in new applications and different locations, sparking concerns about how to solve these issues and what the full impact will be. In the past, variation in semiconductors was considered a foundry issue, typically at the most advanced process node, and largely ignored by most companies. New p... » read more

Dealing With Resistance In Chips
By Mark LaPedus - 21 Jun, 2018 - Comments: 2

Chipmakers continue to scale the transistor at advanced nodes, but they are struggling to maintain the same pace with the other two critical parts of the device—the contacts and interconnects. That’s beginning to change, however. In fact, at 10nm/7nm, chipmakers are introducing new topologies and materials such as cobalt, which promises to boost the performance and reduce unwanted resist... » read more

Taming Mask Metrology
By Mark LaPedus - 22 Oct, 2015 - Comments: 0

For years the IC industry has worried about a bevy of issues with the photomask. Mask costs are the top concern, but mask complexity, write times and defect inspection are the other key issues for both optical and EUV photomasks. Now, mask metrology, the science of measuring the key parameters on the mask, is becoming a new challenge. On this front, mask makers are concerned about the critic... » read more

Overcoming Shallow Trench Isolation
By Kathryn Ta - 20 Jun, 2013 - Comments: 0

By Kathryn Ta To prevent electrical current leaking between adjacent transistors, state-of-the-art microchips feature shallow trench isolation (STI) to isolate transistors from each other. Key steps in the STI process involve etching a pattern of trenches in the silicon, depositing dielectric materials to fill the trenches, and removing the excess dielectric using technologies such as chemical... » read more

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