AI For Circuit Design Quality, Productivity, And Advanced-Node Mapping

By Steve Brown - 26 Oct, 2023 - Comments: 0

The future of circuit design, encompassing analog, RF/5G, and custom electronic circuits, is set to be revolutionized by the integration of generative AI tools. These advanced tools will not only enhance the quality of designs and boost designer productivity but also facilitate the mapping of designs from older semiconductor process nodes to more advanced nodes such as 3nm and below. This blog ... » read more

Megatrends At DAC

By Ann Mutschler - 17 Jul, 2023 - Comments: 0

Spotting key trends over three days of a semiconductor design conference is a challenge, but some important ones come into focus after attending multiple sessions — AI/ML, chiplet integration, and heterogeneous integration in an SoC and package. Frank Schirrmeister, vice president solutions and business development at Arteris IP, talks about a variety of topics that fit under the DAC umbrella... » read more

What Does 2023 Have In Store For Chip Design?

By Brian Bailey - 26 Jan, 2023 - Comments: 0

Predictions seem to be easier to make during times of stability, but they are no more correct than at any other period. During more turbulent times, fewer people are courageous enough to allow their opinions to be heard. And yet it is often those views that are more well thought through, and even if they turn out not to be true, they often contain some very enlightening ideas. 2022 saw some ... » read more

Virtuoso ADE Assembler

By Cadence - 26 May, 2021 - Comments: 0

Cadence Virtuoso ADE Assembler is an advanced design and simulation environment that extends the capabilities of Virtuoso ADE Explorer, adding all the tests needed to fully verify a design over all operational, process, and environmental conditions. As more analysis is required, users can take incremental advantage of the Virtuoso Variation Option to do more advanced statistical analysis on the... » read more

Custom Designs, Custom Problems

By Ed Sperling - 16 Sep, 2020 - Comments: 0

Semiconductor Engineering sat down to discuss power optimization with Oliver King, CTO at Moortec; João Geada, chief technologist at Ansys; Dino Toffolon, senior vice president of engineering at Synopsys; Bryan Bowyer, director of engineering at Mentor, a Siemens Business; Kiran Burli, senior director of marketing for Arm's Physical Design Group; Kam Kittrell, senior product management group d... » read more

Visually Assisted Layout In Custom Design

By Ed Sperling - 29 Oct, 2019 - Comments: 0

Avina Verma, group director for R&D in Synopsys’ Design Group, explains why visual feedback and graphical guidance are so critical in complex layouts, particularly for mixed-signal environments. » read more

Power Issues Rising For New Applications

By Ann Mutschler - 21 Jan, 2019 - Comments: 0

Managing power in chips is becoming more difficult across a wide range of applications and process nodes, forcing chipmakers and systems companies to rethink their power strategies and address problems much earlier than in the past. While power has long been a major focus in the mobile space, power-related issues now are spreading well beyond phones and laptop computers. There are several re... » read more

Preparing For Bigger Changes Ahead

By Ed Sperling - 21 Dec, 2017 - Comments: 0

The semiconductor industry has undergone a fundamental shift over the past year, and it's one that will redefine chipmaking over the next decade or more. While the focus is still on building the fastest, lowest-power devices, whether that's by shrinking features or packaging them into blazing-fast 2.5D or fan-out configurations, these devices are being customized for specific use cases much ... » read more

Custom Vs. Non-Custom Design

By Ed Sperling - 21 Dec, 2017 - Comments: 1

Semiconductor Engineering sat down to discuss custom designs with Yong Pang, head of North American operations for [getentity id="22217" e_name="Imec"]; Phil Burr, director of portfolio product management for [getentity id="22186" e_name="Arm's"] embedded and automotive groups; Ambar Sarkar, chief technologist at eInfochips; and John Tinson, vice president of sales at Sondrel. What follows are ... » read more

Custom Chip Verification Issues Grow

By Ann Mutschler - 29 Mar, 2017 - Comments: 0

With the transition to finFETs, design conditions have grown more intense. They now include a wider PVT range and less headroom. As a result, electronic systems for applications such as mobile, consumer, and automotive increasingly are becoming more difficult to design due to the exacting performance requirements of these applications. This is particularly evident in custom design, including... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?