tag: CXL Consortium

CXL Thriving As Memory Link
By Karen Heyman - 16 Sep, 2024 - Comments: 0

CXL is emerging from a jumble of interconnect standards as a predictable way to connect memory to various processing elements, as well as to share memory resources within a data center. Compute Express Link is built on a PCI Express foundation and supported by nearly all the major chip companies. It is used to link CPUs, GPUs, FPGAs, and other purpose-built accelerators using serial communic... » read more

Chip Industry Week In Review
By The SE Staff - 17 Nov, 2023 - Comments: 0

By Jesse Allen, Karen Heyman, and Liz Allan Japan's Rapidus and the University of Tokyo are teaming up with France's Leti to meet its previously announced mass production goal of 2nm chips by 2027, and chips in the 1nm range in the 2030s. Rapidus was formed in 2022 with the support of eight Japanese companies — Sony, Kioxia, Denso, NEC, NTT, SoftBank, Toyota, and Mitsubishi's banking arm, ... » read more

CXL: The Future Of Memory Interconnect?
By Karen Heyman - 12 Oct, 2023 - Comments: 1

Momentum for sharing memory resources between processor cores is growing inside of data centers, where the explosion in data is driving the need to be able to scale memory up and down in a way that roughly mirrors how processors are used today. A year after the CXL Consortium and JEDEC signed a memorandum of understanding (MOU) to formalize collaboration between the two organizations, suppor... » read more

CXL Picks Up Steam In Data Centers
By Marie C. Baca - 26 Jan, 2023 - Comments: 0

CXL is gaining traction inside large data centers as a way of boosting utilization of different compute elements, such as memories and accelerators, while minimizing the need for additional racks of servers. But the standard is being extended and modified so quickly that it is difficult to keep up with all the changes, each of which needs to be verified and validated across a growing swath of h... » read more

How Memory Design Optimizes System Performance
By John Koon - 21 Sep, 2022 - Comments: 0

Exponential increases in data and demand for improved performance to process that data has spawned a variety of new approaches to processor design and packaging, but it also is driving big changes on the memory side. While the underlying technology still looks very familiar, the real shift is in the way those memories are connected to processing elements and various components within a syste... » read more

Week In Review: Design, Low Power
By Jesse Allen - 12 Aug, 2022 - Comments: 0

Infineon acquired Industrial Analytics, a provider of AI-enabled industrial equipment monitoring. Its solution can monitor plants for early detection of critical developments, based on analysis and evaluation of vibrations, and evaluate data for both predictive and prescriptive maintenance. "Industrial Analytics has outstanding expertise in the area of predictive analysis for industrial machine... » read more

Week In Review: Design, Low Power
By Jesse Allen - 11 Feb, 2022 - Comments: 0

Nvidia's proposed acquisition of Arm is officially off. The deal faced significant pushback from regulatory agencies in the UK, USA, and Europe, which feared it would reduce or limit competition in areas like data center. Nvidia indicated it would continue working with Arm, and it will retain a 20-year Arm license. (SoftBank will retain the $1.25 billion prepaid by Nvidia.) SoftBank said it wil... » read more

Accelerate Adoption Of High-Speed, Low-Latency, Cache-Coherent Standards Using Formal Verification
By Cadence - 09 Jun, 2021 - Comments: 0

We continue to see huge growth in data and compute demand, fueled by increased global data traffic with the 5G rollout, the prevalence of streaming services, and expanded artificial intelligence and machine learning (AI/ML) applications. Several new industry-standard specifications have emerged in recent years to define the protocols of the underlying electronic components and IP building block... » read more

Week In Review: Design, Low Power
By Jesse Allen - 29 Jan, 2021 - Comments: 0

The CXL Consortium published the Compute Express Link 2.0 specification. CXL is an interconnect that maintains memory coherency between the CPU memory space and memory on attached devices. CXL 2.0 adds support for switching for fan-out to connect to more devices, memory pooling for increased memory utilization efficiency and providing memory capacity on demand, and support for persistent memory... » read more

Week In Review: Design, Low Power
By Jesse Allen - 13 Nov, 2020 - Comments: 0

M&A Synopsys acquired Moortec, a provider of in-chip monitoring technology specializing in process, voltage and temperature (PVT) sensors. Moortec's sensors will be a key component to Synopsys' new Silicon Lifecycle Management (SLM) platform. "This acquisition accelerates the expansion of our SLM platform by providing our customers with a comprehensive data-analytics-driven solution for de... » read more

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