The Week In Review: Manufacturing

By Mark LaPedus - 23 Jun, 2017 - Comments: 0

Chipmakers The NAND market is in flux. Not long ago, troubled Toshiba put its memory unit on the block. Finally, the company has selected a group to buy its memory business. The consortium includes the Innovation Network Corp. of Japan, the Development Bank of Japan and Bain Capital. Rival SK Hynix is also part of the group. Others attempted to bid on the business, including Western Digita... » read more

ASML To Buy Hermes

By Mark LaPedus - 16 Jun, 2016 - Comments: 0

Looking to expand into new markets, ASML Holding has entered into an agreement to acquire e-beam wafer inspection specialist Hermes Microvision (HMI) in a cash transaction valued at 2.75 billion euros (US$3.08 billion). With the proposed acquisition of Taiwan’s HMI, ASML will enter two new markets—-wafer inspection as well as mask inspection for extreme ultraviolet (EUV) lithography. In ... » read more

Is EUV Making Progress?

By Ann Mutschler - 18 Jun, 2015 - Comments: 4

By Ann Steffora Mutschler & Ed Sperling EUV has been promised for a couple of decades, counted on for at least three process nodes on the ITRS roadmap, and considered essential to chip manufacturing since 22nm. Billions of dollars have been invested in R&D, engineering teams from around the world have contributed to its development, and still serious problems persist. Just how close... » read more

Not All Scientific Problems Can Be Solved

By Ed Sperling - 18 Jun, 2015 - Comments: 0

In the early part of the 20th century psychologist Karl Lashley set out to locate and study the engram, the memory storage center for the human brain. He never found it. In fact, he ended up disproving the theory that an engram even exists, which was far more important to the understanding of the brain than if he had proven the existence of an engram. The results of more than six decades of ... » read more

Tighter CD Requires Tighter Laser Bandwidth

By Katherine Derbyshire - 24 Feb, 2015 - Comments: 0

Concerns that the bandwidth of the light source for optical lithography can affect pattern quality are not new. No lens material is completely free from chromatic aberration: the refractive index varies with wavelength, and so different wavelengths will focus at different points. Chromatic aberration became a much less serious concern with the replacement of broadband mercury lamps with lase... » read more

Advanced Lithography: Moore’s Law Moves On

By Marc David Levenson - 20 Mar, 2014 - Comments: 1

Every February, experts in nano patterning technologies converge in San Jose, Calif., to present their road maps, brainstorms and results at the SPIE Advanced Lithography Symposium. This year, there was more confusion than ever, partly the result of sessions in unlabeled (but beautiful) new ballrooms at the Convention Center, but mostly because of industry divergences. There is no longer a s... » read more

Reaching For The Reset Button In Lithography

By Mark LaPedus - 21 Mar, 2013 - Comments: 0

By Mark LaPedus Amid ongoing delays and setbacks, extreme ultraviolet (EUV) lithography and multi-beam e-beam have both missed the 10nm logic node. So for the present, chipmakers must take the brute force route at 10nm by using 193nm immersion with multiple patterning. Now, it’s time to hit the reset button. For the 7nm node, chipmakers currently are lining up the lithographic competition... » read more

Cymer’s EUV Team Has An Exciting Few Months

By Michael Watts - 14 Mar, 2013 - Comments: 0

By Michael P.C. Watts At SPIE Advanced Lithography, Cymer announced some serious progress in EUV source development, one of several highlights. The latest results provided 40W of power in runs over 8 hours that mimicked full productions conditions including dose control. As far as I can tell, 40w translates to around 30 - 300 mm wafers an hour. The Cymer source uses a CO2 laser with 3 ampli... » read more

Optical Lithography, Take Two

By Mark LaPedus - 21 Feb, 2013 - Comments: 0

By Mark LaPedus It’s the worst-kept secret in the industry. Extreme ultraviolet (EUV) lithography has missed the initial stages of the 10nm logic and 1xnm NAND flash nodes. Chipmakers hope to insert EUV by the latter stages of 10nm or by 7nm, but vendors are not counting on EUV in the near term and are preparing their back-up plans. Barring a breakthrough with EUV or other technology, IC ... » read more

Moore’s Law Revisited

By Ed Sperling - 25 Oct, 2012 - Comments: 0

It’s no surprise that Moore’s Law can continue for many more generations. Intel’s road map already extends down to 5nm, most likely with carbon nanotube FETs, tunnel FETs, graphene TSVs and maybe even fully depleted SOI to replace bulk CMOS. The rest of the industry has been hanging back a node or two, gliding on the coattails of what Intel and companies like IBM, Samsung and STMicroel... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?