tag: D2S

Changing The Rules For Chip Scaling
By Ed Sperling - 10 Mar, 2021 - Comments: 0

Aki Fujimura, CEO of D2S, talks with Semiconductor Engineering about the incessant drive for chip density, how to improve that density through other means than just scaling, and why this is so important for the chip industry. » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 26 Feb, 2021 - Comments: 0

Chipmakers and OEMs Several chipmakers have not resumed production in their fabs in Texas for the second consecutive week. This follows power outages due to a major winter storm. As reported, a severe winter storm hit many parts of the United States, including Texas. Last week, utility providers began to prioritize service to residential areas in Austin, Texas. As a result, electricity and ... » read more

Breaking The 2nm Barrier
By Mark LaPedus - 18 Feb, 2021 - Comments: 4

Chipmakers continue to make advancements with transistor technologies at the latest process nodes, but the interconnects within these structures are struggling to keep pace. The chip industry is working on several technologies to solve the interconnect bottleneck, but many of those solutions are still in R&D and may not appear for some time — possibly not until 2nm, which is expected t... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 29 Jan, 2021 - Comments: 0

Packaging and test Intel has invested an additional $475 million in its chip assembly and test manufacturing facility in the Saigon Hi-Tech Park (SHTP) in Vietnam. This takes Intel’s total investment in the Vietnam facility to $1.5 billion. The site assembles and tests Intel’s 5G products and processors. TSMC recently announced a huge increase in capital spending for 2021. A large perce... » read more

New Transistor Structures At 3nm/2nm
By Mark LaPedus - 25 Jan, 2021 - Comments: 12

Several foundries continue to develop new processes based on next-generation gate-all-around transistors, including more advanced high-mobility versions, but bringing these technologies into production is going to be difficult and expensive. Intel, Samsung, TSMC and others are laying the groundwork for the transition from today’s finFET transistors to new gate-all-around field-effect trans... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 31 Dec, 2020 - Comments: 0

Chipmakers and OEMs Third Point, a hedge fund, released a letter, saying that Intel needs to explore its strategic alternatives. This includes the breakup of the chip giant. Obtained by Yahoo and others, the letter says Intel needs to decide “whether Intel should remain an integrated device manufacturer” and should divest certain failed acquisitions. Here’s another analysis of the sit... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 24 Dec, 2020 - Comments: 0

Government and trade The U.S. Bureau of Industry and Security (BIS) has expanded its export control regulations for U.S.-based hi-tech companies. The BIS has added more companies to its “Military End User” (MEU) list. The list involves 103 entities, which includes 58 Chinese and 45 Russian companies. The U.S. government has determined that these companies are “military end users” or th... » read more

Blog Review: Dec. 23
By Jesse Allen - 23 Dec, 2020 - Comments: 0

Cadence's Paul McLellan checks out how Arm is becoming a powerhouse in the server and high-end space with the addition of new R&D and a focus on getting the most out of its architecture. Siemens EDA's Harry Foster continues his look at verification trends in FPGAs by checking out adoption of different simulation and formal technologies. Synopsys' Taylor Armerding looks ahead to 2021 w... » read more

AI And High-NA EUV At 3/2/1nm
By Mark LaPedus - 16 Dec, 2020 - Comments: 1

Semiconductor Engineering sat down to discuss lithography and photomask issues with Bryan Kasprowicz, director of technology and strategy and a distinguished member of the technical staff at Photronics; Harry Levinson, principal at HJL Lithography; Noriaki Nakayamada, senior technologist at NuFlare; and Aki Fujimura, chief executive of D2S. What follows are excerpts of that conversation. To vie... » read more

EUV Challenges And Unknowns At 3nm and Below
By Mark LaPedus - 19 Nov, 2020 - Comments: 1

The chip industry is preparing for the next phase of extreme ultraviolet (EUV) lithography at 3nm and beyond, but the challenges and unknowns continue to pile up. In R&D, vendors are working on an assortment of new EUV technologies, such as scanners, resists, and masks. These will be necessary to reach future process nodes, but they are more complex and expensive than the current EUV pro... » read more

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