tag: D2S

Why Changes In Computing Are Driving Changes In Photomasks
By Ed Sperling - 18 Oct, 2022 - Comments: 0

Aki Fujimura, CEO of D2S, talks with Semiconductor Engineering about massive improvements in computation based upon increased density on chips, and why printing Manhattan shapes on a photomask are no longer sufficient to print high-performance devices with predictable reliability every time. He explains why a discontinuity in EDA physical design has opened the door for printing curvilinear shap... » read more

How To Compare Chips
By Ed Sperling - 15 Sep, 2022 - Comments: 0

Traditional metrics for semiconductors are becoming much less meaningful in the most advanced designs. The number of transistors packed into a square centimeter only matters if they can be utilized, and performance per watt is irrelevant if sufficient power cannot be delivered to all of the transistors. The consensus across the chip industry is that the cost per transistor is rising at each ... » read more

Week In Review: Manufacturing, Test
By Karen Heyman - 19 Aug, 2022 - Comments: 0

The U.S. Commerce Department issued export controls on key technologies, including gallium oxide (Ga2O3) and diamond substrates, which are used at high voltages and temperatures, as well as EDA tools specifically developed for GAA FETs. It's not clear how this will impact EDA companies, because many of the tools that will be used for designing for GAA FETs already are in use today for finFETs. ... » read more

Big Changes In Architectures, Transistors, Materials
By Ed Sperling - 18 Aug, 2022 - Comments: 0

Chipmakers are gearing up for fundamental changes in architectures, materials, and basic structures like transistors and interconnects. The net result will be more process steps, increased complexity for each of those steps, and rising costs across the board. At the leading-edge, finFETs will run out of steam somewhere after the 3nm (30 angstrom) node. The three foundries still working at th... » read more

Scaling, Advanced Packaging, Or Both
By Ed Sperling - 01 Aug, 2022 - Comments: 0

Chipmakers are facing a growing number of challenges and tradeoffs at the leading edge, where the cost of process shrinks is already exorbitant and rising. While it's theoretically possible to scale digital logic to 10 angstroms (1nm) and below, the likelihood of a planar SoC being developed at that nodes appears increasingly unlikely. This is hardly shocking in an industry that has heard pr... » read more

For The Love Of Theatre And Mask-Making
By Jan Willis - 05 Jul, 2022 - Comments: 0

Naoya Hayashi has been a friend and important contributor to the eBeam Initiative from our start over 13 years ago. We’re just one of the many interests he has embraced and championed over his 45 year career at DNP. Now it’s our turn to embrace him and thank him for the wonderful memories as he pursues his next chapter after retiring as the first research fellow from DNP this June. Aki Fuji... » read more

Variation Making Trouble In Advanced Packages
By Ed Sperling - 16 Jun, 2022 - Comments: 2

Variation is becoming increasingly problematic as chip designs become more heterogeneous and targeted by application, making it difficult to identify the root cause of problems or predict what can go wrong and when. Concerns about variation traditionally have been confined to the most advanced nodes, where transistor density is highest and where manufacturing processes are still being fine-t... » read more

High-NA EUV May Be Closer Than It Appears
By Katherine Derbyshire - 16 Jun, 2022 - Comments: 1

High-NA EUV is on track to enable scaling down to the Angstrom level, setting the stage for chips with even higher transistor counts and a whole new wave of tools, materials, and system architectures. At the recent SPIE Advanced Lithography conference, Mark Phillips, director of lithography hardware and solutions at Intel, reiterated the company’s intention to deploy the technology in high... » read more

Who Benefits From Chiplets, And When
By Ed Sperling - 31 May, 2022 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss new packaging approaches and integration issues with Anirudh Devgan, president and CEO of Cadence; Joseph Sawicki, executive vice president of Siemens EDA; Niels Faché, vice president and general manager at Keysight; Simon Segars, advisor at Arm; and Aki Fujimura, chairman and CEO of D2S. This discussion was held in front of a... » read more

The Changing Mask Landscape
By Jan Willis - 19 May, 2022 - Comments: 0

Semiconductor photomasks have undergone some major technology changes in the past few years after relatively minor changes for many years. New technologies such as multi-beam mask writers and extreme ultraviolet (EUV) lithography are major breakthroughs as they ramp into high-volume manufacturing. A new trend related to these technologies is the use of curvilinear features on photomasks. Aki... » read more

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