tag: D2S

Increased Photomask Density And Its Impact On EDA
By Ed Sperling - 13 Dec, 2022 - Comments: 0

The ability to print curvilinear shapes on photomasks can have big repercussions on semiconductor design. Aki Fujimura, CEO of D2S, explains why mask rule checking has been bound by complex design rules, and why curvilinear shapes are important for reducing margin and simplifying the chip design process. » read more

High-NA EUV Complicates EUV Photomask Future
By Jan Willis - 17 Nov, 2022 - Comments: 0

The eBeam Initiative’s 11th annual Luminaries survey in 2022 reported EUV fueling growth of the semiconductor photomask industry while a panel of experts cited a number of complications in moving to High-NA EUV during an event co-located with the SPIE Photomask Technology Conference in late September. Industry luminaries representing 44 companies from across the semiconductor ecosystem partic... » read more

Week In Review: Semiconductor Manufacturing, Test
By Karen Heyman - 04 Nov, 2022 - Comments: 0

Nikkei Asia reports the U.S. is urging allies, including Japan, to restrict exports of advanced semiconductors and related technology to China. The U.S. holds 12% of the global semiconductor market, Japan has a 15% share, while Taiwan and South Korea each have about a 20% share. Some U.S. companies have called for other countries to adopt U.S.-style export curbs, arguing it is unfair for only A... » read more

SiPs: The Best Things in Small Packages
By Laura Peters - 20 Oct, 2022 - Comments: 0

System-in-package (SiP) is quickly emerging as the package option of choice for a growing number of applications and markets, setting off a frenzy of activity around new materials, methodologies, and processes. SiP is an essential packaging platform that integrates multiple functionalities onto a single substrate, which enables lower system cost, design flexibility, and superior electrical p... » read more

2022 Survey: Luminaries Report Positive EUV Impact On Mask Trends
By eBeam Initiative - 19 Oct, 2022 - Comments: 0

The eBeam Initiatives 11th Annual Luminaries Survey from July 2022 shows • EUV viewed as a positive impact for mask revenue • EUV remains the top reason for purchasing multi-beam mask writers • Confidence remains high in ability to make curvilinear masks with availability of multi-beam mask writers less of an issue this year Click here to read the survey results. » read more

Why Changes In Computing Are Driving Changes In Photomasks
By Ed Sperling - 18 Oct, 2022 - Comments: 0

Aki Fujimura, CEO of D2S, talks with Semiconductor Engineering about massive improvements in computation based upon increased density on chips, and why printing Manhattan shapes on a photomask are no longer sufficient to print high-performance devices with predictable reliability every time. He explains why a discontinuity in EDA physical design has opened the door for printing curvilinear shap... » read more

How To Compare Chips
By Ed Sperling - 15 Sep, 2022 - Comments: 0

Traditional metrics for semiconductors are becoming much less meaningful in the most advanced designs. The number of transistors packed into a square centimeter only matters if they can be utilized, and performance per watt is irrelevant if sufficient power cannot be delivered to all of the transistors. The consensus across the chip industry is that the cost per transistor is rising at each ... » read more

Week In Review: Manufacturing, Test
By Karen Heyman - 19 Aug, 2022 - Comments: 0

The U.S. Commerce Department issued export controls on key technologies, including gallium oxide (Ga2O3) and diamond substrates, which are used at high voltages and temperatures, as well as EDA tools specifically developed for GAA FETs. It's not clear how this will impact EDA companies, because many of the tools that will be used for designing for GAA FETs already are in use today for finFETs. ... » read more

Big Changes In Architectures, Transistors, Materials
By Ed Sperling - 18 Aug, 2022 - Comments: 0

Chipmakers are gearing up for fundamental changes in architectures, materials, and basic structures like transistors and interconnects. The net result will be more process steps, increased complexity for each of those steps, and rising costs across the board. At the leading-edge, finFETs will run out of steam somewhere after the 3nm (30 angstrom) node. The three foundries still working at th... » read more

Scaling, Advanced Packaging, Or Both
By Ed Sperling - 01 Aug, 2022 - Comments: 0

Chipmakers are facing a growing number of challenges and tradeoffs at the leading edge, where the cost of process shrinks is already exorbitant and rising. While it's theoretically possible to scale digital logic to 10 angstroms (1nm) and below, the likelihood of a planar SoC being developed at that nodes appears increasingly unlikely. This is hardly shocking in an industry that has heard pr... » read more

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