tag: D2S

High-NA EUV May Be Closer Than It Appears
By Katherine Derbyshire - 16 Jun, 2022 - Comments: 1

High-NA EUV is on track to enable scaling down to the Angstrom level, setting the stage for chips with even higher transistor counts and a whole new wave of tools, materials, and system architectures. At the recent SPIE Advanced Lithography conference, Mark Phillips, director of lithography hardware and solutions at Intel, reiterated the company’s intention to deploy the technology in high... » read more

Who Benefits From Chiplets, And When
By Ed Sperling - 31 May, 2022 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss new packaging approaches and integration issues with Anirudh Devgan, president and CEO of Cadence; Joseph Sawicki, executive vice president of Siemens EDA; Niels Faché, vice president and general manager at Keysight; Simon Segars, advisor at Arm; and Aki Fujimura, chairman and CEO of D2S. This discussion was held in front of a... » read more

The Changing Mask Landscape
By Jan Willis - 19 May, 2022 - Comments: 0

Semiconductor photomasks have undergone some major technology changes in the past few years after relatively minor changes for many years. New technologies such as multi-beam mask writers and extreme ultraviolet (EUV) lithography are major breakthroughs as they ramp into high-volume manufacturing. A new trend related to these technologies is the use of curvilinear features on photomasks. Aki... » read more

New End Markets, More Demand For Complex Chips
By Ed Sperling - 16 May, 2022 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss economic conditions and how that affects chip design with Anirudh Devgan, president and CEO of Cadence; Joseph Sawicki, executive vice president of Siemens EDA; Niels Faché, vice president and general manager at Keysight; Simon Segars, advisor at Arm; and Aki Fujimura, chairman and CEO of D2S. This discussion was held in front... » read more

CEO Outlook: Chip Industry 2022
By Ed Sperling - 02 May, 2022 - Comments: 0

Semiconductor Engineering sat down to discuss broad industry changes and how that affects chip design with Anirudh Devgan, president and CEO of Cadence; Joseph Sawicki, executive vice president of Siemens EDA; Niels Faché, vice president and general manager at Keysight; Simon Segars, advisor at Arm; and Aki Fujimura, chairman and CEO of D2S. This discussion was held in front of a live audience... » read more

Using GPUs In Semiconductor Manufacturing
By Ed Sperling - 25 Apr, 2022 - Comments: 0

Massive simulation and curvilinear shapes are forcing the photomask industry to rethink what types of chips work best. Aki Fujimura, CEO of D2S, talks about what happens when shapes printed on a mask are closer to what actually gets printed, how GPUs can be used to accelerate CPUs in single instruction/multiple data (SIMD) operations, and why pixel data is different from other data. » read more

Curvilinear Photomasks Can Be Made Today
By Jan Willis - 21 Apr, 2022 - Comments: 0

Multi-beam mask writers (MBMWs) and GPU-accelerated curvilinear ILT are enabling curvilinear photomasks to be made today. Despite the benefits of improved process windows, curvilinear photomask adoption is slow. Industry luminaries surveyed by the eBeam Initiative in 2021 ranked photomask inspection and infrastructure as the top barriers to adoption, as shown in figure 1. Yet only 4% say the b... » read more

Photomask Shortages Grow At Mature Nodes
By Mark LaPedus - 21 Apr, 2022 - Comments: 2

A surge in demand for chips at mature nodes, coupled with aging photomask-making equipment at those geometries, are causing significant concern across the supply chain. These issues began to surface only recently, but they are particularly worrisome for photomasks, which are critical for chip production. Manufacturing capacity is especially tight for photomasks at 28nm and above, driving up ... » read more

Strategies For Faster Yield Ramps On 5nm Chips
By Laura Peters - 12 Apr, 2022 - Comments: 0

Leading chipmakers TSMC and Samsung are producing 5nm devices in high volume production and TSMC is forging ahead with plans for first 3nm silicon by year end. But to meet such aggressive targets, engineers must identify defects and ramp yield faster than before. Getting a handle on EUV stochastic defects — non-repeating patterning defects such as microbridges, broken lines, or missing con... » read more

Chiplets Enter The Supercomputer Race
By Mark LaPedus - 17 Mar, 2022 - Comments: 0

Several entities from various nations are racing each other to deliver and deploy chiplet-based exascale supercomputers, a new class of systems that are 1,000x faster than today’s supercomputers. The latest exascale supercomputer CPU and GPU designs mix and match complex dies in advanced packages, adding a new level of flexibility and customization for supercomputers. For years, various na... » read more

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