tag: DARPA

New Spintronics Manufacturing Process, Allowing Scaling Down To Sub-5nm (U. of Minnesota/NIST)
By Technical Paper Link - 20 Mar, 2023 - Comments: 0

A new technical paper titled "Sputtered L10-FePd and its Synthetic Antiferromagnet on Si/SiO2 Wafers for Scalable Spintronics" was published by researchers at University of Minnesota and NIST, with funding by DARPA and others. According to a University of Minnesota summary news article, "The industry standard spintronic material, cobalt iron boron, has reached a limit in its scalability. The... » read more

Week In Review: Manufacturing, Test
By Gregory Haley - 10 Mar, 2023 - Comments: 0

Global semiconductor sales decreased 5.2% month-to-month in January, according to a new report by the Semiconductor Industry Association (SIA). For the year, worldwide chip sales are down 18.5%, with the largest drop in sales by China at 31.6%, followed by the Asia Pacific region at 19.5%, and the Americas at 12.4%. Despite the contraction, companies are increasing investments in manufacturi... » read more

Chip Industry’s Technical Paper Roundup: Feb. 14
By Linda Christensen - 14 Feb, 2023 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=80 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us p... » read more

Week In Review: Semiconductor Manufacturing, Test
By Karen Heyman - 03 Feb, 2023 - Comments: 0

Imec released its semiconductor roadmap, which calls for doubling compute power every six months to handle the data explosion and new data-intensive problems. Imec named five walls (scaling, memory, power, sustainability, cost) that need to be dismantled. The roadmap (below) stretches from 7nm to 0.2nm (2 angstroms) by 2036, and includes four generations of gate-all-around FETs followed by thre... » read more

Week in Review: Design, Low Power
By Jesse Allen - 03 Feb, 2023 - Comments: 0

Intel discontinued its Pathfinder for RISC-V program, according to numerous reports. The program provided a pre-silicon development environment to support IP selection and early-stage software development using Intel FPGA and simulator platforms. "Since Intel will not be providing any additional releases or bug fixes, we encourage you to promptly transition to third-party RISC-V software tools ... » read more

Week In Review: Semiconductor Manufacturing, Test
By Karen Heyman - 27 Jan, 2023 - Comments: 0

Starting in 2025, SEMICON West will move to Phoenix for a five-year annual rotation. And in 2024, it will shift dates from July to October. This year’s conference will still take place July 11 to 13 at the Moscone Center. Phoenix will first host SEMICON West on October 7-9, 2025. Thereafter, it will be held at the Moscone Center in San Francisco on the alternating years and over the long term... » read more

Week In Review: Semiconductor Manufacturing, Test
By Karen Heyman - 06 Jan, 2023 - Comments: 0

TSMC is in advanced talks with key suppliers about setting up its first potential European plant in Dresden, Germany, according to Nikkei Asia. The company held a 3nm volume production and capacity expansion ceremony at its Fab 18. TSMC also is building 3nm capacity at its Arizona site, as well as opening a global R&D Center in the Hsinchu Science Park in the second quarter of 2023, to be ... » read more

Week In Review: Design, Low Power
By Marie C. Baca - 06 Jan, 2023 - Comments: 0

Top Of The News Google announced it will support the RISC-V architecture with the Android open-source operating system. In a keynote at the RISC-V Summit, Lars Bergstrom, Google's director of engineering for the Android Platform Programming Languages, noted that Android currently has more than 3 billion users and the support of more than 24,000 vendors. "We've been following RISC-V for a very ... » read more

MTJ-based Circuits Provide Low-Cost, Energy Efficient Solution For Future Hardware Implementation in SC Algorithms
By Technical Paper Link - 30 Dec, 2022 - Comments: 0

A review paper titled "Review of Magnetic Tunnel Junctions for Stochastic Computing" was published by researchers at University of Minnesota Twin Cities. Funding agencies include Semiconductor Research Corporation (SRC), CAPSL, NIST, DARPA and others. Abstract: "Modern computing schemes require large circuit areas and large energy consumption for neuromorphic computing applications, such as... » read more

Designing And Securing Chips For Outer Space
By Marie C. Baca - 19 Dec, 2022 - Comments: 2

Design considerations for hardware used in space go far beyond radiation hardening. These devices have to perform flawlessly for years, under extreme temperature variations, and potentially banged up by space junk or other particles floating in the void over its projected lifetime. Reliability in space adds a whole different set of design considerations. For example, while it's unlikely anyo... » read more

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