tag: DDR3

Understanding the Interactions of Workloads and DRAM Types: A Comprehensive Experimental Study
By Technical Paper Link - 31 Dec, 2019 - Comments: 0

Abstract "It has become increasingly difficult to understand the complex interaction between modern applications and main memory, composed of DRAM chips. Manufacturers are now selling and proposing many different types of DRAM, with each DRAM type catering to different needs (e.g., high throughput, low power, high memory density). At the same time, the memory access patterns of prevalent and... » read more

Prototype Like A Pro
By Tom De Schutter - 24 Mar, 2016 - Comments: 0

FPGA-based prototyping has been a key prototyping technique for many years. The steady increase in software content and thus the need to verify and validate the SoC in context of the software has resulted in an equally steady increase in its usage. FPGA-based prototyping or physical prototyping, as it is also called, offers a great way to develop software, verify the hardware in context of that... » read more

An Insider’s Guide To Planar And 3D DRAM
By Mark LaPedus - 18 Feb, 2016 - Comments: 0

Semiconductor Engineering sat down to talk about planar DRAMs, 3D DRAMs, scaling and systems design with Charles Slayman, technical leader of engineering at network equipment giant Cisco Systems. What follows are excerpts of that conversation. SE: What types of DRAM do network equipment OEMs look at or buy these days? Slayman: When we look at DRAM, we look at it for networking applicatio... » read more

Tech Talk: DDR4
By Ed Sperling - 17 Aug, 2015 - Comments: 1

Rambus' Ely Tsern digs into the challenges in integrating DDR4 compared with DDR3 and why it will get even more difficult over the next few iterations. [youtube vid=2M6vFweaZ-M] » read more

Fundamental Shifts In Chip Business
By Ed Sperling - 17 Aug, 2015 - Comments: 3

Shifting business models, acquisitions, minority investments and increasing uncertainty are creating fundamental shifts in the semiconductor industry that could redefine who is successful in which markets for years to come. The announcement today that [getentity id="22671" e_name="Rambus"] is developing memory controller chips, expanding its business beyond just creating IP for the memory an... » read more

Architecturally Optimizing Memory Bandwidth
By Ann Mutschler - 27 Mar, 2015 - Comments: 0

Making sure that an SoC’s [getkc id="22" kc_name="memory"] bandwidth is optimized is a crucial part of the design process today given its significance toward overall system performance. There are many ways to approach this issue, and all of them can have a direct bearing on the competitiveness of a chip in terms of both power and performance. So where should you start? “Number one, c... » read more

Higher Frequencies Mean More Memory
By Ann Mutschler - 16 Jan, 2015 - Comments: 0

As SoCs get more complex, whether due to higher frequencies or adding more functionality, there is a spillover effect on bandwidth, [getkc id="22" kc_name="memory"] and power. There is no simple way to just turn up the clock frequency in a complex [getkc id="81" kc_name="SoC"]. That relatively straightforward objective will likely require more power domains, more cores, more ways to move sig... » read more

Memory Architectures Undergo Changes
By Ed Sperling - 22 Aug, 2013 - Comments: 0

By Ed Sperling Memory architectures are taking some new twists. Fueled by multi-core and multiple processors, as well as some speed bumps using existing technology, SoC makers are beginning to rethink how to architect, model and assemble memory to improve speed, lower power and reduce cost. What’s unusual about all of this is that it doesn’t rely on new technology, although there certai... » read more

High Speed PCB Layout: Physical Design Issues Of Highspeed Interfaces
By Various Writers - 28 Jun, 2012 - Comments: 0

Moore’s law, applied to data rates, has pushed PCB circuits so fast that the layout becomes part of the circuit. In designs such as DDR3 and PCIe, the fastest memory and high-speed serial performance comes with very specific physical layout requirements that are not obvious. Unless you are thinking like an RF designer, there are many unexpected challenges to a successful high-speed layout. A ... » read more

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