tag: DDR5

Essential DDR5 Features Designers Must Know
By Vadhiraj Sankaranarayanan - 11 Jun, 2020 - Comments: 2

JEDEC has defined and developed three DDR standards – standard DDR, mobile DDR, and graphic DDR – to help designers meet their memory requirements. DDR5 will support a higher data rate (up to 6400 Mb/s) at a lower I/O Voltage (1.1V) and a higher density (based on 16Gb DRAM dies) than DDR4. DDR5 DRAMs and dual-inline memory modules (DIMMs) are expected to hit the market in 2020. This article... » read more

DDR5: The Next-Generation Technology For High Performance Computing
By Synopsys - 13 May, 2020 - Comments: 1

The rapid growth in real-time data requirements for cloud services, IoT, high-performance servers and workstations, hyperscale data centers and big data has increased pressure on memory suppliers to improve memory density and speed. This pressure has resulted in a need for new memory technology that goes beyond the current DDR4 limit of 16 Gb single die capacity and speed of 3200MT/s. Click ... » read more

DDR PHY Training
By Ed Sperling - 21 Apr, 2020 - Comments: 0

Brett Murdock, senior product marketing manager at Synopsys, explains how to train the DRAM physical layer using firmware, why that is so important for flexibility, and what kinds of issues engineers encounter when using this approach. » read more

Enterprise-Class DRAM Reliability
By Ed Sperling - 06 Mar, 2020 - Comments: 0

Brett Murdock, product manager for memory interfaces at Synopsys, examines demand for DDR5 and DDR4 in both on-premise and cloud implementations, what features are available for which versions, how they affect performance and power, how ECC is implemented, and how the data moves throughout these systems. » read more

An Increasingly Complicated Relationship With Memory
By Brian Bailey - 27 Feb, 2020 - Comments: 4

The relationship between a processor and its memory used to be quite simple, but in modern SoCs there are multiple heterogeneous processors and accelerators, each needing a different means of accessing memory for maximum efficiency. Compromises are being made in order to preserve the unified programming model of the past, but the pressures are increasing for some fundamental changes. It does... » read more

What’s Next For High Bandwidth Memory
By Mark LaPedus - 17 Dec, 2019 - Comments: 1

A surge in data is driving the need for new IC package types with more and faster memory in high-end systems. But there are a multitude of challenges on the memory, packaging and other fronts. In systems, for example, data moves back and forth between the processor and DRAM, which is the main memory for most chips. But at times this exchange causes latency and power consumption, sometimes re... » read more

Pushing Memory Harder
By Brian Bailey - 14 Oct, 2019 - Comments: 4

In an optimized system, no component is waiting for another component while there is useful work to be done. Unfortunately, this is not the case with the processor/memory interface. Put simply, memory cannot keep up. Accessing memory is slow, and it can consume a significant fraction of the power budget. And the general consensus is this problem is not going away anytime soon, despite effort... » read more

Why DRAM Won’t Go Away
By Ed Sperling - 18 Sep, 2019 - Comments: 0

Semiconductor Engineering sat down to talk about DRAM's future with Frank Ferro, senior director of product management at Rambus; Marc Greenberg, group director for product marketing at Cadence; Graham Allan, senior product marketing manager for DDR PHYs at Synopsys; and Tien Shiah, senior manager for memory marketing at Samsung Electronics. What follows are excerpts of that conversation. Part ... » read more

DRAM Tradeoffs: Speed Vs. Energy
By Ed Sperling - 31 Jul, 2019 - Comments: 1

Semiconductor Engineering sat down to talk about new DRAM options and considerations with Frank Ferro, senior director of product management at Rambus; Marc Greenberg, group director for product marketing at Cadence; Graham Allan, senior product marketing manager for DDR PHYs at Synopsys; and Tien Shiah, senior manager for memory marketing at Samsung Electronics. What follows are excerpts of th... » read more

Using High-Bandwidth Memory
By Ed Sperling - 01 Oct, 2018 - Comments: 0

eSilicon’s Tim Horel talks about HBM, what engineers need to know to work with this technology, and how it integrates with ASICs at advanced nodes. https://youtu.be/0Yq2XHGF6UE » read more

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