tag: debug

Bringing a Sharper World In Focus With Virtual UHD Verification
By Mentor, a Siemens Business - 11 May, 2016 - Comments: 0

UHD-4K designs require a verification solution that can handle longer, larger frames, faster frame rates, richer colors, wider contrasts, and highly complex chips. Emulation has the speed, capacity, and performance to churn very quickly through the massive amounts of data and long sequences required for verification. Visualization tools are needed to understand and debug what’s going on in UH... » read more

Bridging Hardware And Software
By Ann Mutschler - 28 Apr, 2016 - Comments: 1

The barriers between hardware and software design and verification are breaking down with more intricately integrated systems, bringing together different disciplines and tools. But there are lingering questions about exactly what this shift means design methodologies, team interactions, and what kind of training will be required in the future. Playing heavily into this is the fact that toda... » read more

Better Heterogeneous CPU Designs
By Ronan Synnott - 28 Apr, 2016 - Comments: 0

The trend toward heterogeneous CPU designs is growing. Case in point: The NXP i.MX7 family of devices have such a design. In this blog, I will discuss the (simple) steps necessary to get the most out of i.MX7 using the ARM Development Studio, more commonly known as DS-5, but the information applies to most similar systems. Compiling code depends greatly on the use case. Within DS-5, there... » read more

SoC Verification Made Easy
By Aldec - 27 Apr, 2016 - Comments: 0

As designs grow larger, the time spent verifying a project is growing longer as well. As a solution, some companies are trying to ‘shift-left’ their schedules. Verification via software simulators is not fast enough for large System-on-Chip (SoC) design projects, there-fore one option is to use an FPGA emulator to speed up the design process. But what happens when a bug occurs? This docu... » read more

It’s Transition Time
By Ed Sperling - 24 Mar, 2016 - Comments: 1

For the past couple of years we've been hearing about the coming onslaught of the IoT, difficulties in scaling device features and a shift left that will redefine verification, debug and software prototyping. It's all happening. Taken individually, these are noteworthy changes. Taken as a whole, they represent a massive repositioning of the semiconductor industry, from architectural explorat... » read more

A Formal Transformation
By Brian Bailey - 24 Mar, 2016 - Comments: 0

A very important change is underway in functional verification. In the past, this was an esoteric technology and one that was difficult to deploy. It was relegated to tough problems late in the verification cycle, and it was difficult to justify the ROI unless the technology actually did find some problems. But all of that has changed. Formal verification companies started to use the technology... » read more

Seeing Debug for What It Is
By Neil Johnson - 29 Feb, 2016 - Comments: 0

Debug is problem solving. For many hardware developers, debug is a purpose. Finding a bug is a victory! Heck, debug can be flat out heroic. I’m sure we can all think back to colleagues that put in a few 80 hour, coffee fueled weeks, with managers peering over both shoulders, to fix an insidious string of bugs that threatened to further demolish a broken schedule and sabotage tape-out. W... » read more

Getting Formal About Debug
By Brian Bailey - 25 Feb, 2016 - Comments: 0

While much of the design and verification flows have been automated, debug remains the problem child. It has defied automation and presents a management nightmare due to the variability of the process. In recent articles about debug, we examined how much time development teams spend in the debug process and some of the reasons why it is becoming a bigger problem. This includes issues such as ex... » read more

UVM: It’s Organized And Systematic
By Henry Chan - 25 Feb, 2016 - Comments: 0

One of the reasons I like using UVM is its tendency toward an organized structure and uniformity. Some may find it annoying to adhere to such a strict format in UVM, but I think it’s a good way to keep the basics of UVM engrained in your brain. You always want a good foundation and development of strong fundamentals in any endeavor. Verification is no different and UVM hammers the fundamental... » read more

Debug: Last Bastion Of Automation
By Brian Bailey - 27 Jan, 2016 - Comments: 0

There have been a number of times when anecdotal evidence became folk law and then over time, the effort was put in to find out whether there was any truth in it. Perhaps the most famous case is the statement that verification consumes 70% of development time and resources. For years this “fact” was used in almost every verification presentation and yet nobody knew where the number had come... » read more

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