tag: debug

Manage Your Risk In RISC-V
By Peter Shields - 06 Dec, 2022 - Comments: 0

Adoption of RISC-V processors is accelerating. This technology, like everything, comes with benefits and risks. The open standard means freedom for many developers, but success depends on the development of a support ecosystem around RISC-V. Industry collaboration is making broad adoption of RISC-V possible, and one example is the introduction of efficient trace for RISC-V cores. When incorp... » read more

Bug-Free Designs
By Brian Bailey - 27 Oct, 2022 - Comments: 0

It is possible in theory to create a design with no bugs, but it's impractical, unnecessary, and extremely difficult to prove for bugs you care about. The problem is intractable because the potential state space is enormous for any practical design. The industry has devised ways to handle this complexity, but each has limitations, makes assumptions, and employs techniques that abstract the p... » read more

Debug This! How To Simplify Coverage Analysis And Closure
By Yara Essam - 10 Oct, 2022 - Comments: 0

For years the process of ASIC and FPGA design and verification debug consisted primarily of comprehending the structure and source code of the design with waveforms showing activity over time, based on testbench stimulus. Today, functional verification is exponentially complex with the emergence of new layers of design requirements (beyond basic functionality) that did not exist years ago — f... » read more

Verification Methodologies Evolve, But Slowly
By Brian Bailey - 29 Sep, 2022 - Comments: 0

Semiconductor Engineering sat down to discuss digital twins and what is required to develop and verify new chips across a variety of industries, such as automotive and aerospace, with Larry Lapides, vice president of sales for Imperas Software; Mike Thompson, director of engineering for the verification task group at OpenHW; Paul Graykowski, technical marketing manager for Arteris IP; Shantanu ... » read more

Can ML Help Verification? Maybe
By Brian Bailey - 22 Sep, 2022 - Comments: 0

Functional verification produces an enormous amount of data that could be used to train a machine learning system, but it's not always clear which data is useful or whether it can help. The challenge with ML is understanding when and where to use it, and how to integrate it with other tools and approaches. With a big enough hammer, it is tempting to call everything a nail, and just throwing ... » read more

Recipe To Catch Bugs Faster Using Machine Learning
By Anika Sunda - 19 Sep, 2022 - Comments: 0

We all agree that verification and debug take up a significant amount of time and are arguably the most challenging parts of chip development. Simulator performance has consistently topped the charts and is a critical component in the verification process. Still, the need of the hour is to stretch beyond simulator speed to achieve maximum verification throughput and efficiency. Artificial in... » read more

Better, Faster, And More Efficient Verification With The Power Of AI
By Synopsys - 07 Sep, 2022 - Comments: 0

Verification is often the most challenging part of the chip development process. Verification engineers have to balance quality of results (QOR) with time to results (TTR) and cost of results (COR). AI and ML technologies can play a significant part in increasing QOR, speeding up TTR, and reducing COR. This white paper outlines some of the major challenges for verification, describes how AI pro... » read more

The Power Of Big Data: Or How To Make Perfect 30-Minute Brownies In Only 30 Minutes
By Mark Richards - 27 Jun, 2022 - Comments: 0

You're scrolling online, and the picture stops you in your tracks, grabs you, captivates you. Glistening chocolate pieces are, determinedly yet slowly, oozing down a moist brownie with a crisped-to-perfection, powdered topping. It sits there, confident, flaking lazily onto a bone-white china plate. It looks delicious—mouthwatering—and, apparently, you can make it with just a 30-minute inves... » read more

Enhance IC Reliability Design Verification With Coordinate-Based P2P And CD Checking
By Siemens EDA - 23 Jun, 2022 - Comments: 0

Coordinate-based P2P and CD checks with the Calibre PERC reliability platform enable quick early-stage design verification of ESD protection and other IC reliability issues. Using coordinate-based checking minimizes the amount of rule deck coding required, enabling design teams to start Calibre PERC P2P/CD verification very quickly, and understand and debug the results easily. Because P2P/CD ch... » read more

AI-Powered Verification
By Brian Bailey - 01 Jun, 2022 - Comments: 1

With functional verification consuming more time and effort than design, the chip industry is looking at every possible way to make the verification process more effective and more efficient. Artificial intelligence (AI) and machine learning (ML) are being tested to see how big an impact they can have. While there is progress, it still appears to be just touching the periphery of the problem... » read more

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